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From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv14927/include/asm-mips
Modified Files:
vr41xx-platdep.h
Log Message:
Casio e15 support improvement.
Index: vr41xx-platdep.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr41xx-platdep.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- vr41xx-platdep.h 7 Mar 2002 09:15:17 -0000 1.2
+++ vr41xx-platdep.h 23 Apr 2002 13:14:29 -0000 1.3
@@ -1,11 +1,16 @@
-/* $Id$
- *
+/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Michael Klar
*/
+/*
+ * Changes:
+ * Francois Leblanc <fra...@ce...> Wed, 27 Mar 2002
+ * - Report hardware description in each corresponding header.
+ *
+ */
#ifndef __ASM_MIPS_VR41XX_PLATDEP_H
#define __ASM_MIPS_VR41XX_PLATDEP_H
@@ -50,650 +55,14 @@
* (more to come...)
*/
-#ifdef CONFIG_CASIO_E10
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define FB_X_RES 240
-#define FB_X_VIRTUAL_RES 1024
-#define FB_Y_RES 320
-#define FB_BPP 2
-#define FB_IS_GREY 1
-#endif
-
#ifdef CONFIG_CASIO_E15
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (256 * 1024) /* ??? */
-#define FB_X_RES 240
-#define FB_X_VIRTUAL_RES 512
-#define FB_Y_RES 320
-#define FB_BPP 4
-#define FB_IS_GREY 1
-#define FB_IS_INVERSE 0 //1
-
-// GPIO[27] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- int flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODH |= VR41XX_GIUPIODH_GPIO27; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- int flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODH &= ~VR41XX_GIUPIODH_GPIO27; \
- restore_flags(flags); \
- }
-
-/* LCD control management */
-extern void gpiolcd_setup(void);
-extern int gpiolcd_backlight(int n);
-extern int get_gpiolcd_backlight(void);
-extern int gpiolcd_contrast(int n);
-extern int get_gpiolcd_contrast(void);
-extern int gpiolcd_lcdpower(int on);
-#define LCD_SETUP() gpiolcd_setup()
-#define LCD_BACKLIGHT(n) gpiolcd_backlight(n)
-#define GET_LCD_BACKLIGHT() get_gpiolcd_backlight()
-#define LCD_CONTRAST(n) gpiolcd_contrast(n)
-#define GET_LCD_CONTRAST() get_gpiolcd_contrast()
-#define LCD_POWER(n) gpiolcd_lcdpower(n)
-
-#endif
-
-#ifdef CONFIG_CASIO_E105
-#define VIDEORAM_BASE (KSEG1 + 0x0a200000)
-#define FB_X_RES 240
-#define FB_X_VIRTUAL_RES 256
-#define FB_Y_RES 320
-#define FB_BPP 16
-#endif
-
-#ifdef CONFIG_COMPAQ_AERO_15XX
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
-#define FB_X_RES 320
-#define FB_Y_RES 240
-#define FB_BPP 4
-#define FB_IS_GREY 1
-#define FB_IS_INVERSE 1
-#define GPIO_BTN_MAP { 0, BTN_AP5, 0, 0, 0, 0, 0, \
- BTN_EXIT, BTN_POWER, BTN_AP4, BTN_AP3, BTN_AP2, BTN_AP1, 0, \
- 0, 0, BTN_UP, BTN_DOWN, BTN_ACTION, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= (VR41XX_GIUPODATL_GPIO33 | \
- VR41XX_GIUPODATL_GPIO34); \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~(VR41XX_GIUPODATL_GPIO33 | \
- VR41XX_GIUPODATL_GPIO34); \
- restore_flags(flags); \
- }
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO15;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO15;
-#endif
-
-#ifdef CONFIG_COMPAQ_AERO_21XX
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define DEVICE_IRQ_MASKL 0xfffb
-#define DEVICE_IRQ_MASKH 0xffff
-#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
-#define FB_X_RES 320
-#define FB_Y_RES 240
-#define FB_BPP 8
-#endif
-
-#ifdef CONFIG_EVEREX_FREESTYLE
-#define DEVICE_IRQ_MASKL 0xfffb
-#define DEVICE_IRQ_MASKH 0xffff
-#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
-#define VIDEORAM_SIZE (256 * 1024)
-#define FB_X_RES 320
-#define FB_Y_RES 240
-#define FB_BPP 4
-#define FB_IS_GREY 1
-#define FB_IS_INVERSE 1
-#define GPIO_BTN_MAP { 0, BTN_AP5, 0, 0, BTN_UP, BTN_DOWN, BTN_ACTION, \
- BTN_EXIT, BTN_CONTRAST, BTN_AP1, BTN_AP2, BTN_AP3, BTN_AP4, 0, \
- 0, 0, 0, 0, 0, 0, BTN_BACKLIGHT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
-#define GPIO_BTN_PRESS_LOW
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPODATH |= VR41XX_GIUPODATH_GPIO48;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPODATH &= ~VR41XX_GIUPODATH_GPIO48;
-
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_IBM_WORKPAD
-#define DEVICE_IRQ_MASKL 0xffff
-#define DEVICE_IRQ_MASKH 0x0000
-#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000)
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define FB_X_RES 640
-#define FB_Y_RES 480
-#define FB_BPP 16
-#define GPIO_BTN_MAP { 0, BTN_AP5, BTN_NOTIFICATION, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
-#define GPIO_BTN_PRESS_LOW
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATH |= VR41XX_GIUPODATH_GPIO49; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATH &= ~VR41XX_GIUPODATH_GPIO49; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_AGENDA_VR3
-#define GPIO_BTN_MAP { \
- 0, 0, 0, 0, 0, 0, 0, BTN_PEN, \
- BTN_SYNC, BTN_BATT_DOOR, 0, BTN_POWER_GPIO, 0, 0, 0, 0 \
-}
-#undef GPIO_BTN_PRESS_LOW
-#define VR41XX_ENABLE_IRDA() irda_power(1);
-#define VR41XX_DISABLE_IRDA() irda_power(0);
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GPDATHREG |= VR41XX_GPDATHREG_GPIO19; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GPDATHREG &= ~VR41XX_GPDATHREG_GPIO19; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_NEC_MOBILEPRO_700
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (64 * 1024)
-#define FB_X_VIRTUAL_RES 1024
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 2
-#define FB_IS_GREY 1
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_NEC_MOBILEPRO_750C
-#define VIDEORAM_BASE (KSEG1 + 0x13000000)
-#define FB_X_VIRTUAL_RES 1024
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 8
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_NEC_MOBILEPRO_770
-// Tested by Jean-Nicolas, thanks!
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 800
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 16
-// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_NEC_MOBILEPRO_800
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define FB_X_RES 800
-#define FB_Y_RES 600
-#define FB_BPP 16
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#endif
-
-#ifdef CONFIG_NEC_OSPREY
-// AP4 did strange things, Backlight button GPIO currently used for IOCS16,
-// AP2 used for debug board Ethernet controller, AP3 just doesn't work
-#define GPIO_BTN_MAP { BTN_CONTRAST, BTN_UP, BTN_DOWN, 0, BTN_AP1, BTN_EXIT, 0, \
- 0, BTN_ACTION, 0, 0, 0, 0, 0, 0, 0 }
-#undef GPIO_BTN_PRESS_LOW
-#endif
-
-#ifdef CONFIG_NEC_UEB30
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define FB_X_RES 640
-#define FB_Y_RES 480
-#define FB_BPP 8
-#endif
-
-#ifdef CONFIG_VADEM_CLIO_1000
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO42;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO42;
-#define KBD_SCANLINES 8
-#endif
-
-#ifdef CONFIG_VADEM_CLIO_1050
-#define KBD_SCANLINES 8
-#define VIDEORAM_BASE (KSEG1 + 0x0a200000)
-#define FB_X_RES 640
-#define FB_Y_RES 480
-#define FB_BPP 16
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R300
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (64 * 1024)
-#define FB_X_VIRTUAL_RES 1024
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 2
-#define FB_IS_GREY 1
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R320
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (64 * 1024)
-#define FB_X_VIRTUAL_RES 640
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 2
-#define FB_IS_GREY 1
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R430
-#define DEVICE_IRQ_MASKL 0xffff
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a180100)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 640
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 16
-// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPODATL_GPIO46;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPODATL_GPIO46;
-#endif
-
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R500
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x13000000)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 1024
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 8
-// #define FB_IS_GRAY 1
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R510
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 1024
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 8
-// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R520
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 800
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 16
-// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14;
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R530
-#define DEVICE_IRQ_MASKL 0xffff
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a180100)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 640
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 16
-// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPODATL_GPIO46;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPODATL_GPIO46;
-#endif
-
-#ifdef CONFIG_DOCOMO_SIGMARION
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 640
-#define FB_X_RES 640
-#define FB_Y_RES 240
-#define FB_BPP 16
-// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \
- restore_flags(flags); \
- }
-// GPIO[14] is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPIODL |= VR41XX_GIUPODATL_GPIO46;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPODATL_GPIO46;
-#endif
-
-#ifdef CONFIG_NEC_MOBILEGEAR2_R700
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
-#define VIDEORAM_SIZE (640 * 240 * 8)
-#define FB_X_VIRTUAL_RES 800
-#define FB_X_RES 800
-#define FB_Y_RES 600
-#define FB_BPP 16
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-// PODAT[14](GPIO[46]) is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO46;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO46;
+#include <asm/vr41xx/e15.h>
#endif
-#ifdef CONFIG_NEC_MOBILEGEAR2_R730
-// Not tested yet
-#define DEVICE_IRQ_MASKH 0x0000
-#define VIDEORAM_BASE (KSEG1 + 0x0a0ea600)
-#define VIDEORAM_SIZE (800 * 600 * 16)
-#define FB_X_VIRTUAL_RES 800
-#define FB_X_RES 800
-#define FB_Y_RES 600
-#define FB_BPP 16
-// GPIO[12] is speaker power on/off bit
-#define VR41XX_ENABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-#define VR41XX_DISABLE_SPEAKER() \
- { \
- unsigned long flags; \
- save_and_cli(flags); \
- *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \
- restore_flags(flags); \
- }
-// PODAT[14](GPIO[46]) is serial power on/off bit
-#define VR41XX_ENABLE_SERIAL(x) \
- *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO46;
-#define VR41XX_DISABLE_SERIAL(x) \
- *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO46;
+#ifdef CONFIG_CASIO_E55
+#include <asm/vr41xx/e55.h>
#endif
-#ifdef CONFIG_NEC_HARRIER
-#define VIDEORAMBASE (KSEG1 + 0x10400000)
-#define FB_X_RES 800
-#define FB_Y_RES 600
-#define FB_BPP 8
-#define VIDEORAM_SIZE (FB_X_RES * FB_Y_RES * FB_BPP / 8)
-#define KBD_SCANLINES 8
-#define GPIO_BTN_MAP { \
- BTN_AP1, 0, 0, BTN_AP2, \
- 0, 0, 0, BTN_BACKLIGHT, \
- 0, BTN_AP3, 0, 0, \
- BTN_AP4, 0, 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, 0, 0, \
- 0, 0, 0, 0, \
- BTN_AP25, BTN_AP26, BTN_AP27, BTN_AP28, \
- BTN_AP29, BTN_AP30, BTN_AP31, BTN_AP32, \
- BTN_AP33, BTN_AP34, BTN_AP35, BTN_AP36 \
- }
-#endif
// Some reasonable defaults
|
|
From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4111/casio-e15
In directory usw-pr-cvs1:/tmp/cvs-serv14927/arch/mips/vr41xx/vr4111/casio-e15
Modified Files:
Makefile setup.c
Added Files:
ide-e15.c
Log Message:
Casio e15 support improvement.
--- NEW FILE: ide-e15.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* IDE routines for typical pc-like standard configurations
* for the CASIO CASSIOPEIA E-55/65.
*
* Copyright (C) 1998, 1999, 2001 by Ralf Baechle
*/
/*
* Changes:
* Yoichi Yuasa <yu...@hh...> Sun, 24 Feb 2002
* - Added CASIO CASSIOPEIA E-55/65 support.
*
* Francois Leblanc <fra...@ce...> Mon, 25 Mar 2002
* - Just rename E55 en E15 for Casio E15 Support.
* - Set only 0xc170 io base valid to start more quickly.
*/
#include <linux/sched.h>
#include <linux/ide.h>
#include <linux/ioport.h>
#include <linux/hdreg.h>
#include <asm/ptrace.h>
#include <asm/hdreg.h>
static int e15_ide_default_irq(ide_ioreg_t base)
{
return 40;
}
static ide_ioreg_t e15_ide_default_io_base(int index)
{
switch (index) {
case 0: return 0xc170;
case 1: return 0;
case 2: return 0;
case 3: return 0;
case 4: return 0;
case 5: return 0;
}
return 0;
}
static void e15_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port,
ide_ioreg_t ctrl_port, int *irq)
{
ide_ioreg_t reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port) {
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
} else {
hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206;
}
if (irq != NULL)
*irq = 0;
hw->io_ports[IDE_IRQ_OFFSET] = 0;
}
static int e15_ide_request_irq(unsigned int irq,
void (*handler)(int,void *, struct pt_regs *),
unsigned long flags, const char *device,
void *dev_id)
{
return request_irq(irq, handler, flags, device, dev_id);
}
static void e15_ide_free_irq(unsigned int irq, void *dev_id)
{
free_irq(irq, dev_id);
}
static int e15_ide_check_region(ide_ioreg_t from, unsigned int extent)
{
return check_region(from, extent);
}
static void e15_ide_request_region(ide_ioreg_t from, unsigned int extent,
const char *name)
{
request_region(from, extent, name);
}
static void e15_ide_release_region(ide_ioreg_t from, unsigned int extent)
{
release_region(from, extent);
}
struct ide_ops e15_ide_ops = {
&e15_ide_default_irq,
&e15_ide_default_io_base,
&e15_ide_init_hwif_ports,
&e15_ide_request_irq,
&e15_ide_free_irq,
&e15_ide_check_region,
&e15_ide_request_region,
&e15_ide_release_region
};
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4111/casio-e15/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- Makefile 22 Mar 2002 10:22:43 -0000 1.3
+++ Makefile 23 Apr 2002 13:14:29 -0000 1.4
@@ -21,6 +21,7 @@
obj-y += setup.o prom.o
obj-$(CONFIG_REMOTE_DEBUG) += gdb.o
+obj-$(CONFIG_IDE) += ide-e15.o
include $(TOPDIR)/Rules.make
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4111/casio-e15/setup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- setup.c 22 Mar 2002 10:22:43 -0000 1.4
+++ setup.c 23 Apr 2002 13:14:29 -0000 1.5
@@ -16,8 +16,8 @@
*/
/*
* Changes:
- * - Francois Leblanc <fra...@ce...>
- * Copy from casio-e55/setup.c an update to casio-e15.
+ * Francois Leblanc <fra...@ce...> Wed, 26 Mar 2002
+ * - Copy from casio-e55/setup.c an update to casio-e15.
*
*/
#include <linux/config.h>
@@ -42,7 +42,7 @@
#endif
#ifdef CONFIG_BLK_DEV_IDE
-extern struct ide_ops std_ide_ops;
+extern struct ide_ops e15_ide_ops;
#endif
struct semaphore vr41xx_dma_sem;
@@ -72,11 +72,11 @@
#endif
#ifdef CONFIG_PM_SUSPEND_WAKEUP
-#include <asm/vr41xx-platdep.h>
#include <asm/gdb-stub.h>
+extern asmlinkage void kernel_entry(void);
+
extern void breakpoint(void);
-extern void kernel_entry(void);
extern void DbgInitSerial(void);
// Put contents of WINCE_SIGNATURE_CHECK1 & 2 at
@@ -93,6 +93,7 @@
static unsigned int wince_signature_old2;
static unsigned int wince_return_old;
+/* avoid use of sp in this routine since sp isn't correctly set yet*/
static asmlinkage void casio_e15_wakeup(void)
{
write_32bit_cp0_register(CP0_STATUS, ST0_CU0);
@@ -107,21 +108,29 @@
*WINCE_SIGNATURE_ADD2 = wince_signature_old2;
*WINCE_RETURN_ADD = wince_return_old;
-#ifdef CONFIG_REMOTE_DEBUG
- //re-init serial
- set_debug_traps();
- DbgInitSerial();
-#endif
-
- //try restore screen view
- gpiolcd_lcdpower(1);
-
#ifdef CONFIG_VR41XX_LED
- vr41xx_xblink_led(2, 12, 3);
+ if (*VR41XX_LEDCNTREG & 0x0001)
+ return; // Now blinking, so ignore this request
+ *VR41XX_LEDHTSREG = 12; // LED on time (1 = 0.0625 sec)
+ *VR41XX_LEDLTSREG = 3; // LED off time (1 = 0.0625 sec)
+ *VR41XX_LEDASTCREG = 2; // How many times blink
+ *VR41XX_LEDCNTREG = 0x0002; // Enable auto stop
+ *VR41XX_LEDCNTREG |= 0x0001; // Start blinking
+ // Wait for LEDINT
+ while ((*VR41XX_LEDINTREG & 0x0001) == 0);
+ // Clear LEDINT
+ *VR41XX_LEDINTREG = 0x0001;
#endif
// restart kernel
- kernel_entry();
+ asm volatile (
+ " .set noreorder\n"
+ " j kernel_entry\n"
+ " nop\n"
+ " nop\n"
+ " nop\n"
+ " .set reorder\n"
+ );
}
void vr41xx_extend_hibernate(void)
@@ -162,7 +171,7 @@
board_timer_setup = vr41xx_timer_setup;
#ifdef CONFIG_BLK_DEV_IDE
- ide_ops = &std_ide_ops;
+ ide_ops = &e15_ide_ops;
#endif
#ifdef CONFIG_FB
|
|
From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv14927/drivers/char
Modified Files:
Config.in buttons.c e105btns.c gpiobtns.c
Log Message:
Casio e15 support improvement.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.34
retrieving revision 1.35
diff -u -d -r1.34 -r1.35
--- Config.in 18 Mar 2002 22:35:50 -0000 1.34
+++ Config.in 23 Apr 2002 13:14:29 -0000 1.35
@@ -93,6 +93,16 @@
bool ' Enable Touch Panel Interface Unit Support' CONFIG_VRC4173_PIU
fi
fi
+if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
+ tristate 'VR touch panel driver support' CONFIG_TOUCH_PANEL y
+ tristate 'VR buttons driver support' CONFIG_BUTTONS y
+ if [ "$CONFIG_BUTTONS" = "y" ]; then
+ tristate ' GPIO buttons support' CONFIG_VR41XX_GPIO_BUTTONS
+ tristate ' E105 buttons support' CONFIG_VR41XX_E105_BUTTONS
+ tristate ' Direct power off support' CONFIG_BUTTONS_DIRECT_POWEROFF
+ fi
+ tristate 'A/D interface support' CONFIG_ADIF
+fi
if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
fi
Index: buttons.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/buttons.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- buttons.c 7 Mar 2002 09:15:16 -0000 1.1
+++ buttons.c 23 Apr 2002 13:14:29 -0000 1.2
@@ -5,11 +5,16 @@
* SMP-safe. VR41xx CPUs don't support SMP anyway.
*
* Copyright (c) 2000 Michael Klar <wyl...@in...>
- * Copyright (c) 2001 François Leblanc <fra...@ce...>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
+ */
+/*
+ * Changes:
+ * Francois Leblanc <fra...@ce...> Wed, 27 Mar 2002
+ * - Add print version to follow updates.
+ *
*/
#include <linux/kernel.h>
Index: e105btns.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/e105btns.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- e105btns.c 7 Mar 2002 09:15:16 -0000 1.1
+++ e105btns.c 23 Apr 2002 13:14:29 -0000 1.2
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
* Casio E-10x/50x input button (sub)driver
*
* Original driver by Robert Coie, modified and integrated into main VR41xx
Index: gpiobtns.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/gpiobtns.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- gpiobtns.c 7 Mar 2002 09:15:16 -0000 1.1
+++ gpiobtns.c 23 Apr 2002 13:14:29 -0000 1.2
@@ -1,5 +1,4 @@
-/* $Id$
- *
+/*
* GPIO button functions for VR41xx button input driver
*
* Note that the way this driver does atomic access to buffers is not
@@ -45,12 +44,12 @@
#endif
struct gpiobtns_device {
- struct timer_list btn_timer;
- btn_mask_t btn_timer_data;
- btn_mask_t btn_state;
- btn_mask_t btn_bounce;
- btn_mask_t pending_bits;
- unsigned char press_low;
+ struct timer_list btn_timer;
+ btn_mask_t btn_timer_data;
+ btn_mask_t btn_state;
+ btn_mask_t btn_bounce;
+ btn_mask_t pending_bits;
+ unsigned char press_low;
};
#ifdef GPIO_BTN_PRESS_LOW
|
|
From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv14927/arch/mips/configs Modified Files: defconfig-casio-e15 Log Message: Casio e15 support improvement. Index: defconfig-casio-e15 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-casio-e15,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- defconfig-casio-e15 22 Mar 2002 10:22:43 -0000 1.3 +++ defconfig-casio-e15 23 Apr 2002 13:14:28 -0000 1.4 @@ -47,6 +47,7 @@ # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set # CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1100 is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_HP_LASERJET is not set # CONFIG_HIGHMEM is not set @@ -65,13 +66,7 @@ CONFIG_SERIAL=y CONFIG_SERIAL_MANY_PORTS=y CONFIG_DUMMY_KEYB=y -CONFIG_TOUCH_PANEL=y -CONFIG_BUTTONS=y -CONFIG_VR41XX_GPIO_BUTTONS=y -CONFIG_VR41XX_E105_BUTTONS=y -# CONFIG_BUTTONS_DIRECT_POWEROFF is not set CONFIG_VR41XX_LED=y -CONFIG_ADIF=y CONFIG_GPIO_LCD=y CONFIG_VR41XX_EXTEND_HIBERNATE=y CONFIG_EISA=y @@ -79,7 +74,9 @@ # # Loadable module support # -# CONFIG_MODULES is not set +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y # # CPU selection @@ -118,30 +115,20 @@ CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y +CONFIG_BINFMT_MISC=m CONFIG_PM=y CONFIG_PM_SUSPEND_WAKEUP=y CONFIG_PM_POWERED_SUSPEND=y # CONFIG_PM_STANDBY is not set CONFIG_PROC_GIUINFO=y -CONFIG_MOUNT_PROC=y +# CONFIG_MOUNT_PROC is not set # CONFIG_CPU_FREQ is not set CONFIG_NET=y -CONFIG_HOTPLUG=y - -# -# PCMCIA/CardBus support -# +# CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set - -# -# PCI Hotplug Support -# # CONFIG_HOTPLUG_PCI is not set -# CONFIG_HOTPLUG_PCI_COMPAQ is not set -# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_BSD_PROCESS_ACCT=y CONFIG_SYSCTL=y # @@ -169,8 +156,8 @@ # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_INITRD=y @@ -191,18 +178,18 @@ # # Networking options # -CONFIG_PACKET=y +CONFIG_PACKET=m CONFIG_PACKET_MMAP=y -CONFIG_NETLINK_DEV=y +# CONFIG_NETLINK_DEV is not set # CONFIG_NETFILTER is not set # CONFIG_FILTER is not set -CONFIG_UNIX=y +CONFIG_UNIX=m CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_BOOTP is not set # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set @@ -300,7 +287,7 @@ # ARCnet devices # # CONFIG_ARCNET is not set -CONFIG_DUMMY=y +CONFIG_DUMMY=m # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set @@ -338,15 +325,18 @@ # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PLIP is not set -CONFIG_PPP=y +CONFIG_PPP=m CONFIG_PPP_MULTILINK=y # CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPPOE=y -# CONFIG_SLIP is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPPOE=m +CONFIG_SLIP=m +# CONFIG_SLIP_COMPRESSED is not set +# CONFIG_SLIP_SMART is not set +# CONFIG_SLIP_MODE_SLIP6 is not set # # Wireless LAN (non-hamradio) @@ -374,10 +364,10 @@ # # IrDA (infrared) support # -CONFIG_IRDA=y -CONFIG_IRLAN=y -CONFIG_IRNET=y -CONFIG_IRCOMM=y +CONFIG_IRDA=m +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m # CONFIG_IRDA_ULTRA is not set # CONFIG_IRDA_CACHE_LAST_LSAP is not set # CONFIG_IRDA_FAST_RR is not set @@ -386,8 +376,8 @@ # # Infrared-port device drivers # -CONFIG_IRTTY_SIR=y -CONFIG_IRPORT_SIR=y +CONFIG_IRTTY_SIR=m +CONFIG_IRPORT_SIR=m # CONFIG_DONGLE is not set # CONFIG_USB_IRDA is not set # CONFIG_NSC_FIR is not set @@ -417,6 +407,12 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_TOUCH_PANEL=y +CONFIG_BUTTONS=y +CONFIG_VR41XX_GPIO_BUTTONS=y +# CONFIG_VR41XX_E105_BUTTONS is not set +# CONFIG_BUTTONS_DIRECT_POWEROFF is not set +CONFIG_ADIF=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -429,10 +425,7 @@ # Mice # # CONFIG_BUSMOUSE is not set -CONFIG_MOUSE=y -CONFIG_PSMOUSE=y -# CONFIG_82C710_MOUSE is not set -# CONFIG_PC110_PAD is not set +# CONFIG_MOUSE is not set # # Joysticks @@ -447,7 +440,7 @@ # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set -# CONFIG_MIPS_RTC is not set +CONFIG_MIPS_RTC=m # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -468,8 +461,8 @@ # File systems # # CONFIG_QUOTA is not set -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -483,7 +476,7 @@ # CONFIG_JBD_DEBUG is not set CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y -CONFIG_UMSDOS_FS=y +# CONFIG_UMSDOS_FS is not set CONFIG_VFAT_FS=y # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set @@ -519,13 +512,14 @@ # # CONFIG_CODA_FS is not set # CONFIG_INTERMEZZO_FS is not set -CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y -CONFIG_LOCKD=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_ROOT_NFS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +CONFIG_SUNRPC=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y # CONFIG_SMB_FS is not set # CONFIG_NCP_FS is not set # CONFIG_NCPFS_PACKET_SIGNING is not set @@ -646,18 +640,15 @@ # CONFIG_FBCON_VGA_PLANES is not set # CONFIG_FBCON_VGA is not set # CONFIG_FBCON_HGA is not set -CONFIG_FBCON_FONTWIDTH8_ONLY=y -CONFIG_FBCON_FONTS=y +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set +# CONFIG_FBCON_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set # # Sound # -CONFIG_SOUND=y +CONFIG_SOUND=m # CONFIG_SOUND_BT878 is not set # CONFIG_SOUND_CMPCI is not set # CONFIG_SOUND_EMU10K1 is not set |
|
From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/common
In directory usw-pr-cvs1:/tmp/cvs-serv14927/arch/mips/vr41xx/common
Modified Files:
giuinfo.c power.c
Log Message:
Casio e15 support improvement.
Index: giuinfo.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/common/giuinfo.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- giuinfo.c 7 Mar 2002 09:15:16 -0000 1.1
+++ giuinfo.c 23 Apr 2002 13:14:28 -0000 1.2
@@ -10,7 +10,11 @@
* for more details.
*
*/
-
+/*
+ * Changes:
+ * Francois Leblanc <fra...@ce...> Wed, 04 apr 2002
+ * - Add more info view.
+ */
#include <linux/kernel.h>
#include <linux/proc_fs.h>
#include <linux/init.h>
@@ -76,13 +80,31 @@
*VR41XX_MISCREG13, *VR41XX_MISCREG14, *VR41XX_MISCREG15);
#else
len = sprintf(page,
- "giuiosell: 0x%04hx\n"
- "giuioselh: 0x%04hx\n"
- "giupiodl: 0x%04hx\n"
- "giupiodh: 0x%04hx\n"
- "giupodatl: 0x%04hx\n",
+ "giuiosell: 0x%04hx\n"
+ "giuioselh: 0x%04hx\n"
+ "giupiodl: 0x%04hx\n"
+ "giupiodh: 0x%04hx\n"
+ "giupodatl: 0x%04hx\n"
+ "\n"
+ "giupodath: 0x%04hx\n"
+ "giuintstatl: 0x%04hx\n"
+ "giuintstath: 0x%04hx\n"
+ "giuintenl: 0x%04hx\n"
+ "giuintenh: 0x%04hx\n"
+ "giuinttypl: 0x%04hx\n"
+ "giuinttyph: 0x%04hx\n"
+ "giuintalsell: 0x%04hx\n"
+ "giuintalselh: 0x%04hx\n"
+ "giuinthtsell: 0x%04hx\n"
+ "giuinthtselh: 0x%04hx\n"
+ "giuusepdn: 0x%04hx\n"
+ "giutermupdn: 0x%04hx\n",
*VR41XX_GIUIOSELL, *VR41XX_GIUIOSELH, *VR41XX_GIUPIODL,
- *VR41XX_GIUPIODH, *VR41XX_GIUPODATL);
+ *VR41XX_GIUPIODH, *VR41XX_GIUPODATL, *VR41XX_GIUPODATH,
+ *VR41XX_GIUINTSTATL, *VR41XX_GIUINTSTATH, *VR41XX_GIUINTENL,
+ *VR41XX_GIUINTENH, *VR41XX_GIUINTTYPL, *VR41XX_GIUINTTYPH,
+ *VR41XX_GIUINTALSELL, *VR41XX_GIUINTALSELH, *VR41XX_GIUINTHTSELL,
+ *VR41XX_GIUINTHTSELH, *VR41XX_GIUUSEUPDN, *VR41XX_GIUTERMUPDN);
#endif
if (len <= off+count) *eof = 1;
Index: power.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/common/power.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- power.c 22 Mar 2002 10:22:43 -0000 1.2
+++ power.c 23 Apr 2002 13:14:28 -0000 1.3
@@ -3,14 +3,19 @@
* PM User interface loosely based on Andrew Henroid's i386 ACPI driver
*
* Copyright (C) 2000 Michael Klar
- * Copyright (C) 2002 François Leblanc <fra...@ce...>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
-
+/*
+ * Changes:
+ * Francois Leblanc <fra...@ce...> Wed, 27 Mar 2002
+ * - Add extend hibernate function to let board manage specific
+ * actions before hibernate like casio E15 witch update win ce
+ * memory signature before halt and so reboot in linux.
+ */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/config.h>
@@ -164,6 +169,8 @@
// never reached...
}
+extern void DbgInitSerial(void);
+
asmlinkage int do_wakeup(void)
{
int i, retval;
@@ -186,6 +193,13 @@
*(MIN_GPIOREG + i) = gpio_state[i];
do_pm_irq_request(PM_RESUME);
retval = pm_send_all(PM_RESUME, (void *)0);
+
+#ifdef CONFIG_REMOTE_DEBUG
+ //re-init serial
+ set_debug_traps();
+ DbgInitSerial();
+#endif
+
if (!retval) {
sti();
up(&vr41xx_dma_sem);
|
|
From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr41xx
In directory usw-pr-cvs1:/tmp/cvs-serv14927/include/asm-mips/vr41xx
Modified Files:
e15.h
Log Message:
Casio e15 support improvement.
Index: e15.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr41xx/e15.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- e15.h 19 Mar 2002 14:22:21 -0000 1.1
+++ e15.h 23 Apr 2002 13:14:29 -0000 1.2
@@ -7,14 +7,18 @@
*
* Copyright 2002 Yoichi Yuasa
* yu...@hh...
- * Copyright 2002 francois Leblanc <fra...@ce...>
*
- *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
+/*
+ * Changes:
+ * Francois Leblanc <fra...@ce...> Wed, 27 Mar 2002
+ * - Report dependant config from vr41xx-platdep.h here.
+ *
+ */
#ifndef __CASIO_E15_H
#define __CASIO_E15_H
@@ -30,10 +34,62 @@
#define VR41XX_ISA_IO_BASE 0x14000000
#define VR41XX_ISA_IO_SIZE 0x04000000
-#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
-#define IO_PORT_RESOURCE_START 0
-#define IO_PORT_RESOURCE_END VR41XX_ISA_IO_SIZE
-#define IO_MEM_RESOURCE_START VR41XX_ISA_MEM_BASE
-#define IO_MEM_RESOURCE_END (VR41XX_ISA_MEM_BASE + VR41XX_ISA_MEM_SIZE)
+#define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE)
+#define IO_PORT_RESOURCE_START 0
+#define IO_PORT_RESOURCE_END VR41XX_ISA_IO_SIZE
+#define IO_MEM_RESOURCE_START VR41XX_ISA_MEM_BASE
+#define IO_MEM_RESOURCE_END (VR41XX_ISA_MEM_BASE + VR41XX_ISA_MEM_SIZE)
+
+/*
+ * Board specific hardware description
+ */
+#define VIDEORAM_BASE (KSEG1 + 0x0a000000)
+#define VIDEORAM_SIZE (256 * 1024) /* ??? */
+#define FB_X_RES 240
+#define FB_X_VIRTUAL_RES 512
+#define FB_Y_RES 320
+#define FB_BPP 4
+#define FB_IS_GREY 1
+#define FB_IS_INVERSE 0 //1
+
+// GPIO[27] is speaker power on/off bit
+#define VR41XX_ENABLE_SPEAKER() \
+ { \
+ int flags; \
+ save_and_cli(flags); \
+ *VR41XX_GIUPIODH |= VR41XX_GIUPIODH_GPIO27; \
+ restore_flags(flags); \
+ }
+#define VR41XX_DISABLE_SPEAKER() \
+ { \
+ int flags; \
+ save_and_cli(flags); \
+ *VR41XX_GIUPIODH &= ~VR41XX_GIUPIODH_GPIO27; \
+ restore_flags(flags); \
+ }
+
+/*
+ * LCD control management
+ */
+extern void gpiolcd_setup(void);
+extern int gpiolcd_backlight(int n);
+extern int get_gpiolcd_backlight(void);
+extern int gpiolcd_contrast(int n);
+extern int get_gpiolcd_contrast(void);
+extern int gpiolcd_lcdpower(int on);
+#define LCD_SETUP() gpiolcd_setup()
+#define LCD_BACKLIGHT(n) gpiolcd_backlight(n)
+#define GET_LCD_BACKLIGHT() get_gpiolcd_backlight()
+#define LCD_CONTRAST(n) gpiolcd_contrast(n)
+#define GET_LCD_CONTRAST() get_gpiolcd_contrast()
+#define LCD_POWER(n) gpiolcd_lcdpower(n)
+
+/* GPIO buttons mapping from GPIO0 to GPIO31 */
+#define GPIO_BTN_MAP { \
+ 0, 0, 0, 0, 0, BTN_POWER_GPIO, BTN_ACTION, BTN_EXIT, \
+ BTN_AP3, BTN_AP2, BTN_AP1, BTN_AP4, BTN_UP, BTN_DOWN, BTN_SYNC, \
+ 0, 0, BTN_NOTIFICATION, 0, BTN_NOTIFICATION, 0, 0, 0, \
+ 0, 0, 0, 0, 0, BTN_NORTH, BTN_WEST, BTN_EAST \
+}
#endif /* __CASIO_E15_H */
|
|
From: Leblanc f. <fle...@us...> - 2002-04-23 13:14:33
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv14927/arch/mips
Modified Files:
config.in
Log Message:
Casio e15 support improvement.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.94
retrieving revision 1.95
diff -u -d -r1.94 -r1.95
--- config.in 21 Apr 2002 20:56:23 -0000 1.94
+++ config.in 23 Apr 2002 13:14:28 -0000 1.95
@@ -489,13 +489,7 @@
define_bool CONFIG_SERIAL y
define_bool CONFIG_SERIAL_MANY_PORTS y
define_bool CONFIG_DUMMY_KEYB y
- define_bool CONFIG_TOUCH_PANEL y
- define_bool CONFIG_BUTTONS y
- define_bool CONFIG_VR41XX_GPIO_BUTTONS y
- define_bool CONFIG_VR41XX_E105_BUTTONS y
- define_bool CONFIG_BUTTONS_DIRECT_POWEROFF n
define_bool CONFIG_VR41XX_LED y
- define_bool CONFIG_ADIF y
define_bool CONFIG_GPIO_LCD y
define_bool CONFIG_VR41XX_EXTEND_HIBERNATE y
fi
|
|
From: Pete P. <pp...@us...> - 2002-04-22 23:28:54
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv23818/include/asm-mips Modified Files: pb1000.h pb1100.h pb1500.h Log Message: Added support for the 2nd pcmcia slot on the Pb1000 board. Index: pb1000.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pb1000.h,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- pb1000.h 15 Feb 2002 19:47:28 -0000 1.7 +++ pb1000.h 22 Apr 2002 23:28:51 -0000 1.8 @@ -28,7 +28,8 @@ #define __ASM_PB1000_H /* PCMCIA PB1000 specific defines */ -#define PCMCIA_MAX_SOCK 0 /* the second socket, 1, is not supported at this time */ +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) #define PB1000_PCR 0xBE000000 #define PCR_SLOT_0_VPP0 (1<<0) Index: pb1100.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pb1100.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- pb1100.h 18 Apr 2002 00:03:28 -0000 1.2 +++ pb1100.h 22 Apr 2002 23:28:51 -0000 1.3 @@ -77,6 +77,7 @@ /* PCMCIA PB1100 specific defines */ #define PCMCIA_MAX_SOCK 0 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) /* VPP/VCC */ #define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) Index: pb1500.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pb1500.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- pb1500.h 15 Feb 2002 19:47:28 -0000 1.2 +++ pb1500.h 22 Apr 2002 23:28:51 -0000 1.3 @@ -41,6 +41,7 @@ /* PCMCIA PB1500 specific defines */ #define PCMCIA_MAX_SOCK 0 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) /* VPP/VCC */ #define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) |
|
From: Pete P. <pp...@us...> - 2002-04-22 23:28:53
|
Update of /cvsroot/linux-mips/linux/drivers/pcmcia
In directory usw-pr-cvs1:/tmp/cvs-serv23818/drivers/pcmcia
Modified Files:
au1000_generic.c au1000_pb1x00.c
Log Message:
Added support for the 2nd pcmcia slot on the Pb1000 board.
Index: au1000_generic.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/pcmcia/au1000_generic.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- au1000_generic.c 19 Apr 2002 19:12:52 -0000 1.10
+++ au1000_generic.c 22 Apr 2002 23:28:50 -0000 1.11
@@ -183,6 +183,11 @@
memset(pcmcia_socket, 0,
sizeof(struct au1000_pcmcia_socket) * socket_count);
+ /*
+ * Assuming max of 2 sockets, which the Au1000 supports.
+ * WARNING: the Pb1000 has two sockets, and both work, but you
+ * can't use them both at the same time due to glue logic conflicts.
+ */
for(i=0; i < socket_count; i++) {
if(pcmcia_low_level->socket_state(i, &state)<0){
@@ -199,8 +204,10 @@
pcmcia_socket[i].phys_mem = (memaddr_t)0xF80000000;
}
else {
- printk(KERN_ERR "au1000: socket 1 not supported\n");
- return 1;
+ pcmcia_socket[i].virt_io =
+ (u32)ioremap((ioaddr_t)0xF08000000, 0x1000);
+ pcmcia_socket[i].phys_attr = (memaddr_t)0xF48000000;
+ pcmcia_socket[i].phys_mem = (memaddr_t)0xF88000000;
}
}
Index: au1000_pb1x00.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/pcmcia/au1000_pb1x00.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- au1000_pb1x00.c 22 Apr 2002 17:37:35 -0000 1.2
+++ au1000_pb1x00.c 22 Apr 2002 23:28:50 -0000 1.3
@@ -68,12 +68,12 @@
static int pb1x00_pcmcia_init(struct pcmcia_init *init)
{
#ifdef CONFIG_MIPS_PB1000
- u32 pcr;
+ u16 pcr;
pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
- writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
+ writew(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
au_sync_delay(100);
- writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
+ writew(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
au_sync();
pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
@@ -81,8 +81,7 @@
writew(pcr, PB1000_PCR);
au_sync_delay(20);
- /* There's two sockets, but only the first one, 0, is used and tested */
- return 1;
+ return PCMCIA_NUM_SOCKS;
#else /* fixme -- take care of the Pb1500 at some point */
@@ -91,7 +90,7 @@
pcr &= ~(PB1100_PC_DEASSERT_RST | PB1100_PC_DRV_EN);
writew(pcr, PB1100_MEM_PCMCIA);
au_sync_delay(500);
- return 1;
+ return PCMCIA_NUM_SOCKS;
#endif
}
@@ -118,16 +117,18 @@
static int
pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
{
- u32 inserted;
- unsigned char vs;
+ u32 inserted0, inserted1;
+ unsigned short vs0, vs1;
#ifdef CONFIG_MIPS_PB1000
- vs = readw(PB1000_ACR1);
- inserted = !(vs & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
- vs = (vs >> 4) & 0x3;
+ vs0 = vs1 = readw(PB1000_ACR1);
+ inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
+ inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2));
+ vs0 = (vs0 >> 4) & 0x3;
+ vs1 = (vs1 >> 12) & 0x3;
#else
- vs = (readw(PB1100_BOARD_STATUS) >> 4) & 0x3;
- inserted = !((readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */
+ vs0 = (readw(PB1100_BOARD_STATUS) >> 4) & 0x3;
+ inserted0 = !((readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */
#endif
state->ready = 0;
@@ -136,8 +137,8 @@
state->detect = 0;
if (sock == 0) {
- if (inserted) {
- switch (vs) {
+ if (inserted0) {
+ switch (vs0) {
case 0:
case 2:
state->vs_3v=1;
@@ -147,14 +148,29 @@
default:
/* return without setting 'detect' */
printk(KERN_ERR "pb1x00 bad VS (%d)\n",
- vs);
+ vs0);
return;
}
state->detect = 1;
}
}
else {
- printk(KERN_ERR "pb1x00 socket_state bad sock %d\n", sock);
+ if (inserted1) {
+ switch (vs1) {
+ case 0:
+ case 2:
+ state->vs_3v=1;
+ break;
+ case 3: /* 5V */
+ break;
+ default:
+ /* return without setting 'detect' */
+ printk(KERN_ERR "pb1x00 bad VS (%d)\n",
+ vs1);
+ return;
+ }
+ state->detect = 1;
+ }
}
if (state->detect) {
@@ -173,11 +189,11 @@
if(info->sock > PCMCIA_MAX_SOCK) return -1;
- if(info->sock == 0) {
- info->irq = PCMCIA_IRQ;
- }
- else
- info->irq = -1;
+ /*
+ * Even in the case of the Pb1000, both sockets are connected
+ * to the same irq line.
+ */
+ info->irq = PCMCIA_IRQ;
return 0;
}
|
|
From: Pete P. <pp...@us...> - 2002-04-22 23:28:53
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv23818/arch/mips/configs Modified Files: defconfig-pb1000 defconfig-pb1100 Log Message: Added support for the 2nd pcmcia slot on the Pb1000 board. Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.21 retrieving revision 1.22 diff -u -d -r1.21 -r1.22 --- defconfig-pb1000 22 Apr 2002 17:45:00 -0000 1.21 +++ defconfig-pb1000 22 Apr 2002 23:28:50 -0000 1.22 @@ -2,6 +2,7 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y +CONFIG_MIPS32=y # # Code maturity level options Index: defconfig-pb1100 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1100,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- defconfig-pb1100 19 Apr 2002 19:12:52 -0000 1.6 +++ defconfig-pb1100 22 Apr 2002 23:28:50 -0000 1.7 @@ -2,6 +2,7 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y +CONFIG_MIPS32=y # # Code maturity level options @@ -470,8 +471,8 @@ # IrDA protocols # CONFIG_IRLAN=m -CONFIG_IRNET=m -# CONFIG_IRCOMM is not set +# CONFIG_IRNET is not set +CONFIG_IRCOMM=m # CONFIG_IRDA_ULTRA is not set # |
|
From: Pete P. <pp...@us...> - 2002-04-22 18:03:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv31694/arch/mips/kernel
Modified Files:
setup.c
Log Message:
Fixed up the Pb1x00 power management.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.57
retrieving revision 1.58
diff -u -d -r1.57 -r1.58
--- setup.c 22 Apr 2002 16:37:35 -0000 1.57
+++ setup.c 22 Apr 2002 17:45:01 -0000 1.58
@@ -156,6 +156,12 @@
cpu_wait = sr7100_wait;
printk(" errata work around.\n");
break;
+ case CPU_AU1000:
+ case CPU_AU1100:
+ case CPU_AU1500:
+ cpu_wait = au1k_wait;
+ printk(" available.\n");
+ break;
default:
printk(" unavailable.\n");
break;
|
|
From: Pete P. <pp...@us...> - 2002-04-22 18:03:14
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv31694/include/asm-mips Modified Files: processor.h Log Message: Fixed up the Pb1x00 power management. Index: processor.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/processor.h,v retrieving revision 1.12 retrieving revision 1.13 diff -u -d -r1.12 -r1.13 --- processor.h 19 Jan 2002 21:17:35 -0000 1.12 +++ processor.h 22 Apr 2002 17:45:02 -0000 1.13 @@ -44,6 +44,7 @@ extern void r39xx_wait(void); extern void r4k_wait(void); extern void sr7100_wait(void); +extern void au1k_wait(void); extern struct cpuinfo_mips cpu_data[]; extern unsigned int vced_count, vcei_count; |
|
From: Pete P. <pp...@us...> - 2002-04-22 18:03:13
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv31694/arch/mips/au1000/common
Modified Files:
Makefile power.c
Log Message:
Fixed up the Pb1x00 power management.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- Makefile 15 Feb 2002 19:47:24 -0000 1.8
+++ Makefile 22 Apr 2002 17:45:00 -0000 1.9
@@ -19,9 +19,9 @@
O_TARGET := au1000.o
-export-objs = prom.o serial.o clocks.o
+export-objs = prom.o serial.o clocks.o power.o
-obj-y := prom.o int-handler.o dma.o irq.o puts.o time.o reset.o power.o clocks.o
+obj-y := prom.o int-handler.o dma.o irq.o puts.o time.o reset.o clocks.o power.o
obj-$(CONFIG_AU1000_UART) += serial.o
obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
Index: power.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/power.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- power.c 15 Feb 2002 19:47:24 -0000 1.5
+++ power.c 22 Apr 2002 17:45:00 -0000 1.6
@@ -49,7 +49,7 @@
# define DPRINTK(fmt, args...)
#endif
-inline void au1_wait(void);
+inline void au1k_wait(void);
static void calibrate_delay(void);
extern void set_au1000_speed(unsigned int new_freq);
@@ -138,7 +138,7 @@
if (retval)
return retval;
suspend_mode = 1;
- au1_wait();
+ au1k_wait();
retval = pm_send_all(PM_RESUME, (void *) 0);
}
return retval;
@@ -278,7 +278,7 @@
__initcall(pm_init);
-inline void au1_wait(void)
+inline void au1k_wait(void)
{
__asm__(".set\tmips3\n\t"
"wait\n\t"
@@ -333,7 +333,7 @@
#else /* CONFIG_PM */
-void au1_wait(void)
+void au1k_wait(void)
{
__asm__("nop\n\t" "nop\n\t");
}
|
|
From: Pete P. <pp...@us...> - 2002-04-22 18:03:09
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv31694/arch/mips/configs Modified Files: defconfig-pb1000 Log Message: Fixed up the Pb1x00 power management. Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.20 retrieving revision 1.21 diff -u -d -r1.20 -r1.21 --- defconfig-pb1000 19 Apr 2002 19:10:17 -0000 1.20 +++ defconfig-pb1000 22 Apr 2002 17:45:00 -0000 1.21 @@ -95,7 +95,7 @@ # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_RC32300 is not set CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_ADVANCED=y CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_LLDSCD is not set @@ -445,7 +445,49 @@ # # IrDA (infrared) support # -# CONFIG_IRDA is not set +CONFIG_IRDA=y + +# +# IrDA protocols +# +CONFIG_IRLAN=m +# CONFIG_IRNET is not set +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +# CONFIG_IRTTY_SIR is not set +# CONFIG_IRPORT_SIR is not set + +# +# Dongle support +# +# CONFIG_DONGLE is not set + +# +# FIR device drivers +# +# CONFIG_USB_IRDA is not set +# CONFIG_NSC_FIR is not set +# CONFIG_WINBOND_FIR is not set +# CONFIG_TOSHIBA_FIR is not set +CONFIG_AU1000_FIR=m +# CONFIG_SMC_IRCC_FIR is not set +# CONFIG_ALI_FIR is not set +# CONFIG_VLSI_FIR is not set # # ISDN subsystem |
|
From: Pete P. <pp...@us...> - 2002-04-22 17:37:39
|
Update of /cvsroot/linux-mips/linux/drivers/pcmcia In directory usw-pr-cvs1:/tmp/cvs-serv28003/drivers/pcmcia Modified Files: au1000_pb1x00.c Log Message: Fixed a Pb1000 voltage sense bug which I introduced when I merged the Pb1x00 files. Index: au1000_pb1x00.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/pcmcia/au1000_pb1x00.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- au1000_pb1x00.c 19 Apr 2002 19:12:52 -0000 1.1 +++ au1000_pb1x00.c 22 Apr 2002 17:37:35 -0000 1.2 @@ -124,6 +124,7 @@ #ifdef CONFIG_MIPS_PB1000 vs = readw(PB1000_ACR1); inserted = !(vs & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2)); + vs = (vs >> 4) & 0x3; #else vs = (readw(PB1100_BOARD_STATUS) >> 4) & 0x3; inserted = !((readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */ |
|
From: Paul M. <le...@us...> - 2002-04-22 16:37:40
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv30310/kernel Modified Files: setup.c Log Message: nec_korva_setup() -> nec_vr41xx_setup. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v retrieving revision 1.56 retrieving revision 1.57 diff -u -d -r1.56 -r1.57 --- setup.c 21 Apr 2002 19:30:07 -0000 1.56 +++ setup.c 22 Apr 2002 16:37:35 -0000 1.57 @@ -735,7 +735,6 @@ void momenco_ocelot_setup(void); void nino_setup(void); void nec_osprey_setup(void); - void nec_korva_setup(void); void ps2_setup(void); void jmr3927_setup(void); void it8172_setup(void); @@ -833,11 +832,6 @@ #ifdef CONFIG_NEC_OSPREY case MACH_GROUP_NEC_VR41XX: nec_osprey_setup(); - break; -#endif -#ifdef CONFIG_NEC_KORVA - case MACH_GROUP_NEC_VR41XX: - nec_korva_setup(); break; #endif #ifdef CONFIG_CPU_VR41XX |
|
From: Paul M. <le...@us...> - 2002-04-22 16:37:40
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva
In directory usw-pr-cvs1:/tmp/cvs-serv30310/korva
Modified Files:
setup.c
Log Message:
nec_korva_setup() -> nec_vr41xx_setup.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/setup.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- setup.c 2 Jan 2002 19:12:16 -0000 1.8
+++ setup.c 22 Apr 2002 16:37:35 -0000 1.9
@@ -90,9 +90,9 @@
extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
#endif
-void __init nec_korva_setup(void)
+void __init nec_vr41xx_setup(void)
{
- //MIPS_DEBUG(printk("nec_korva_setup() starts.\n"));
+ //MIPS_DEBUG(printk("nec_vr41xx_setup() starts.\n"));
#if defined(CONFIG_BLK_DEV_INITRD)
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
|
|
From: Paul M. <le...@us...> - 2002-04-21 20:56:26
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv19938/arch/mips/cobalt
Modified Files:
Makefile int-handler.S irq.c pci.c promcon.c setup.c
Added Files:
via.c
Log Message:
Make cobalt work again. (Hopefully the end of OSS syncing for today.)
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/Makefile,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- Makefile 6 Jan 2002 00:07:31 -0000 1.14
+++ Makefile 21 Apr 2002 20:56:23 -0000 1.15
@@ -17,8 +17,9 @@
O_TARGET := cobalt.o
obj-y += rtc_dallas.o irq.o int-handler.o \
- reset.o setup.o ide.o
+ reset.o setup.o ide.o via.o
+obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_NEW_PCI) += pci_ops.o pci_fixups.o
obj-$(CONFIG_REMOTE_DEBUG) += promcon.o
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/int-handler.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- int-handler.S 19 Dec 2001 01:07:25 -0000 1.5
+++ int-handler.S 21 Apr 2002 20:56:23 -0000 1.6
@@ -1,42 +1,24 @@
/*
- * arch/mips/cobalt/int-handler.S
+ * Cobalt interrupt handler
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
*/
+
+#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
+#include <asm/cobalt/cobalt.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/*
- * Descriptions of interrupts on different typs of Cobalt MIPS-based products.
- *
- * Qube1:
- * H/W int0: Galileo CPU interrupt (pin 61)
- * H/W int1: Coprocessor interrupt
- * H/W int2: Ethernet interrupt
- * H/W int3: Spare
- * H/W int4: VIA interrupt (pin 145)
- * H/W int5: Galileo PCI interrupt (pin 196)
- * H/W NMI: VIA NMI (pin 146)
- *
- * RaQ1:
- * H/W int0: Galileo CPU interrupt (pin 61)
- * H/W int1: Ethernet interrupt
- * H/W int2: 2nd Ethernet interrupt
- * H/W int3: Serial interrupt
- * H/W int4: VIA interrupt (pin 145)
- * H/W int5: Galileo PCI interrupt (pin 196)
- * H/W NMI: VIA NMI (pin 146)
- *
- * Qube2/RaQ2:
- * H/W int0: Galileo CPU interrupt (pin 61)
- * H/W int1: Ethernet interrupt
- * H/W int2: 2nd ethernet interrupt
- * H/W int3: Serial interrupt
- * H/W int4: VIA interrupt
- * H/W int5: Galileo PCI interrupt (pin 196)
- * H/W NMI: VIA NMI (pin 146)
- *
- * cobalt_handle_int: Interrupt handler for the twenty-seven board.
+ * cobalt_handle_int: Interrupt handler for Cobalt boards
*/
.text
.set noreorder
@@ -45,139 +27,79 @@
NESTED(cobalt_handle_int, PT_SIZE, sp)
SAVE_ALL
CLI
-
- /*
- * MIPS CPU's store the interrupt information in the CAUSE and STATUS
- * registers. The CAUSE register contains the pending interrupts, and
- * the STATUS register has the current interrupt mask.
- *
- * Interrupt Interrupt CAUSE Pending STATUS Mask
- * Type Number Bit Name Bit Name
- * --------- --------- --- ---- --- ----
- * Software 0 8 IP0 8 IM0
- * Software 1 9 IP1 9 IM1
- * Hardware 0 10 IP2 10 IM2
- * Hardware 1 11 IP3 11 IM3
- * Hardware 2 12 IP4 12 IM4
- * Hardware/
- * Coprocessor 3 13 IP5 13 IM5
- * Hardware 4 14 IP6 14 IM6
- * Hardware/
- * Timer 5 15 IP7 15 IM7
- *
- * So, get the CAUSE and STATUS registers, apply the interrupt mask to
- * the pending interrupts (via an AND)
- * Get pending Interrupts
- */
.set at
/*
* Get pending Interrupts
*/
- mfc0 t0, CP0_CAUSE # get irq mask
- mfc0 t1, CP0_STATUS # get enabled interrupts
- and t0, t1
-
-/* Such a kind of cascade is optimal for R5000 */
-
- andi t1, t0,STATUSF_IP2 /* Check for Galileo timer */
- bnez t1, ll_galileo_irq
+ mfc0 s0,CP0_CAUSE # get irq mask
- andi t1, t0,STATUSF_IP6 /* Check for Via chip */
- bnez t1, ll_via_irq
- andi t1, t0,STATUSF_IP3
- bnez t1, ll_ethernet0_irq
-/*
- * This should be conditional, and not used for the cube-1, but
- * there is not a config flag that is useful.
- */
+ andi a0,s0,CAUSEF_IP2 /* Check for Galileo timer */
+ beq a0,zero,1f
+ andi a0,s0,CAUSEF_IP6 /* Check for Via chip */
- andi t1, t0,STATUSF_IP4
- bnez t1, ll_ethernet1_irq
- andi t1, t0,STATUSF_IP5
- bnez t1, ll_serial_irq
- andi t1, t0,STATUSF_IP7
- bnez t1, ll_pci_irq
+ /* Galileo interrupt */
+ jal galileo_irq
+ move a0,sp
+ j ret_from_irq
nop
- /* wrong alarm ... */
- j spurious_interrupt
- nop
- END(cobalt_handle_int)
+1:
+ beq a0,zero,1f /* Check IP6 */
+ andi a0,s0,CAUSEF_IP3
- .align 5
- .set reorder
- ll_galileo_irq: move a0,sp
- jal cobalt_gt64111_irq
- nop
+ /* Via interrupt */
+ jal via_irq
+ move a0,sp
j ret_from_irq
nop
- .align 5
- .set reorder
-ll_via_irq:
- move a0, sp
- jal cobalt_via_irq
- nop
- j ret_from_irq
- nop
+1:
+ beq a0,zero,1f /* Check IP3 */
+ andi a0,s0,CAUSEF_IP4
- .align 5
- .set reorder
-ll_ethernet0_irq:
- mfc0 s0, CP0_STATUS # mask interrupt
- ori t0, s0, (STATUSF_IP3 | STATUSF_IP4)
- xori t0, (STATUSF_IP3 | STATUSF_IP4)
- mtc0 t0, CP0_STATUS
- li a0, 4
- move a1, sp
+ /* Ethernet 0 interrupt */
+ li a0,4
jal do_IRQ
- nop
- mtc0 s0,CP0_STATUS
+ move a1,sp
+
j ret_from_irq
nop
- .align 5
- .set reorder
-ll_serial_irq:
- li a0,7
- move a1,sp
+1:
+ beq a0,zero,1f /* Check IP4 */
+ andi a0,s0,CAUSEF_IP5
+
+ /* Ethernet 1 interrupt */
+ li a0,13
jal do_IRQ
- nop
+ move a1,sp
+
j ret_from_irq
nop
+1:
+ beq a0,zero,1f /* Check IP5 */
+ andi a0,s0,CAUSEF_IP7
- .align 5
- .set reorder
-ll_ethernet1_irq:
- mfc0 s0, CP0_STATUS # mask interrupt
-
- ori t0, s0, (STATUSF_IP3 | STATUSF_IP4)
- xori t0, (STATUSF_IP3 | STATUSF_IP4)
-
- mtc0 t0, CP0_STATUS
- li a0, 13
- move a1, sp
+ /* Serial interrupt */
+ li a0,7
jal do_IRQ
- nop
- mtc0 s0, CP0_STATUS
+ move a1,sp
+
j ret_from_irq
nop
+1:
+ beq a0,zero,1f /* Check IP7 */
+ nop
-#
-# This is pretty weird. The "pci" interrupt on the hardware
-# skematic is from the PCI side of the galileo, so we would
-# only get interrupts here if WE write the control register
-# that normally enables the cpu to send interrupts to the PCI.
-#
-# If you want to interrupt a PCI card, look elsewhere.
-#
- .align 5
- .set reorder
-ll_pci_irq:
- li a0, 7
- move a1, sp
+ /* PCI interrupt */
+ li a0,9
jal do_IRQ
- nop
+ move a1,sp
+
+1:
j ret_from_irq
nop
+
+ END(cobalt_handle_int)
+
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/irq.c,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- irq.c 2 Jan 2002 18:19:35 -0000 1.13
+++ irq.c 21 Apr 2002 20:56:23 -0000 1.14
@@ -1,104 +1,223 @@
/*
- * Interrupt handling for the VIA ISA bridge.
+ * IRQ vector handles
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
*
- * Everything the same ... just different ...
*/
-#include <linux/init.h>
+
#include <linux/kernel.h>
-#include <asm/atomic.h>
-#include <linux/irq.h>
-#include <asm/cobalt/cobalt.h>
-#include <asm/ptrace.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
+#include <asm/system.h>
-extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
+#include <asm/cobalt/cobalt.h>
+
+/* Cobalt Exception handler */
extern void cobalt_handle_int(void);
-extern void init_i8259_irqs(void);
-#ifdef CONFIG_REMOTE_DEBUG
-extern void set_debug_traps(void);
-extern void breakpoint(void);
-#endif
+/* Via masking routines */
+extern void unmask_irq(unsigned int irqr);
+extern void mask_irq(unsigned int irq);
-#undef DEBUG
-asmlinkage void cobalt_via_irq(struct pt_regs *regs)
-{
- char mstat, sstat;
+/*
+ * We have two types of interrupts that we handle, ones that come
+ * in through the CPU interrupt lines, and ones that come in on
+ * the via chip. The CPU mappings are:
+ * 0,1 - S/W (ignored)
+ * 2 - Galileo chip (timer)
+ * 3 - Tulip 0 + NCR SCSI
+ * 4 - Tulip 1
+ * 5 - 16550 UART
+ * 6 - VIA southbridge PIC
+ * 7 - PCI
+ *
+ * The VIA chip is a master/slave 8259 setup and has the
+ * following interrupts
+ * 8 - RTC
+ * 14 - IDE0
+ * 15 - IDE1
+ *
+ * In the table we use a 1 to indicate that we use a VIA interrupt
+ * line, and IE_IRQx to indicate that we use a CPU interrupt line
+ *
+ * We map all of these onto linux IRQ #s 0-15 and forget the rest
+ */
+#define NOINT_LINE 0
+#define CPUINT_LINE(x) IE_IRQ##x
+#define VIAINT_LINE 1
- /* Read Master Status */
- isa_writeb(0x0C, 0x20);
- mstat = isa_readb(0x20);
+#define COBALT_IRQS 16
-#ifdef DEBUG
- printk("Via: Cause=%x Status=%x mstat=%x ",
- regs->cp0_cause, regs->cp0_status, mstat);
-#endif
+static unsigned short irqnr_to_type[COBALT_IRQS] =
+{ CPUINT_LINE(0), NOINT_LINE, VIAINT_LINE, NOINT_LINE,
+ CPUINT_LINE(1), NOINT_LINE, NOINT_LINE, CPUINT_LINE(3),
+ VIAINT_LINE, CPUINT_LINE(5), NOINT_LINE, NOINT_LINE,
+ NOINT_LINE, CPUINT_LINE(2), VIAINT_LINE, VIAINT_LINE };
- if (mstat < 0) {
- mstat &= 0x7f;
- if (mstat != 2) {
- do_IRQ(mstat, regs);
- isa_writeb(mstat | 0x20, 0x20);
- } else {
- sstat = isa_readb(0xA0);
+/*
+ * Cobalt CPU irq
+ */
- /* Slave interrupt */
- isa_writeb(0x0C, 0xA0);
- sstat = isa_readb(0xA0);
+static void enable_cpu_irq(unsigned int irq)
+{
+ unsigned long flags;
-#ifdef DEBUG
- printk("Via: Cause=%x Status=%x sstat=%x ",
- regs->cp0_cause, regs->cp0_status, sstat);
-#endif
- if (sstat < 0) {
- do_IRQ((sstat + 8) & 0x7f, regs);
- isa_writeb(0x22, 0x20);
- isa_writeb((sstat & 0x7f) | 0x20, 0xA0);
- } else {
- printk("Spurious slave interrupt...\n");
- }
- }
- } else
- printk("Spurious master interrupt...");
+ save_and_cli(flags);
+ change_cp0_status(irqnr_to_type[irq], irqnr_to_type[irq]);
+ restore_flags(flags);
}
-#define GALILEO_INTCAUSE 0xb4000c18
-#define GALILEO_T0EXP 0x00000100
+static unsigned startup_cpu_irq(unsigned int irq)
+{
+ enable_cpu_irq(irq);
-asmlinkage void cobalt_gt64111_irq(struct pt_regs *regs)
+ return 0;
+}
+
+static void disable_cpu_irq(unsigned int irq)
{
- unsigned long irq_src = *((unsigned long *) GALILEO_INTCAUSE);
+ unsigned long flags;
-#if 0
- printk("Galileo: Cause=%x Status=%x IRQsrc=%x\n",
- regs->cp0_cause, regs->cp0_status, irq_src);
-#endif
+ save_and_cli(flags);
+ change_cp0_status(irqnr_to_type[irq], ~(irqnr_to_type[irq]));
+ restore_flags(flags);
+}
- /* Check for timer irq ... */
- if (irq_src & GALILEO_T0EXP) {
- do_IRQ(0, regs);
- *((volatile unsigned long *) GALILEO_INTCAUSE) = 0;
- } else {
- long cause = read_32bit_cp0_register(CP0_CAUSE),
- status = read_32bit_cp0_register(CP0_STATUS);
+#define shutdown_cpu_irq disable_cpu_irq
+#define mask_and_ack_cpu_irq disable_cpu_irq
- printk("Spurious Galileo interrupt...");
- printk("Galileo: Cause=%lx Status=%lx IRQsrc=%lx\n", cause, status, irq_src);
- }
+static void end_cpu_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_cpu_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_cpu_irq_type = {
+ "Cobalt CPU",
+ startup_cpu_irq,
+ shutdown_cpu_irq,
+ enable_cpu_irq,
+ disable_cpu_irq,
+ mask_and_ack_cpu_irq,
+ end_cpu_irq,
+ NULL
+};
+
+
+/*
+ * Cobalt VIA irq
+ */
+
+static void enable_via_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ unmask_irq(irq);
+ restore_flags(flags);
}
+static unsigned startup_via_irq(unsigned int irq)
+{
+ enable_via_irq(irq);
+
+ return 0;
+}
+
+static void disable_via_irq(unsigned int irq)
+{
+ unsigned long flags;
+
+ save_and_cli(flags);
+ mask_irq(irq);
+ restore_flags(flags);
+}
+
+#define shutdown_via_irq disable_via_irq
+#define mask_and_ack_via_irq disable_via_irq
+
+static void end_via_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_via_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_via_irq_type = {
+ "Cobalt VIA",
+ startup_via_irq,
+ shutdown_via_irq,
+ enable_via_irq,
+ disable_via_irq,
+ mask_and_ack_via_irq,
+ end_via_irq,
+ NULL
+};
+
+
+static struct irqaction via_irq2 = {
+ no_action, 0, 0, "slave cascade", NULL, NULL
+};
+
+static struct resource pic1_io_resource = {
+ "VIA PIC Master", 0x20, 0x3f, IORESOURCE_BUSY
+};
+
+static struct resource pic2_io_resource = {
+ "VIA PIC Slave", 0xa0, 0xbf, IORESOURCE_BUSY
+};
+
+
void __init init_IRQ(void)
{
- set_except_vector(0, cobalt_handle_int);
+ int i;
+ /* Initialise all of the IRQ descriptors */
init_generic_irq();
- init_i8259_irqs();
-#ifdef CONFIG_REMOTE_DEBUG
- set_debug_traps();
- breakpoint();
-#endif
+ /* Map the irqnr to the type int we have */
+ for (i=0; i < COBALT_IRQS; i++) {
+ if (irqnr_to_type[i] >= CPUINT_LINE(0))
+ /* cobalt_cpu_irq_type */
+ irq_desc[i].handler = &cobalt_cpu_irq_type;
+ else if (irqnr_to_type[i] == VIAINT_LINE)
+ /* VIA/8259 irq_type */
+ irq_desc[i].handler = &cobalt_via_irq_type;
+ else {} /* Leave it as disabled/no handler */
+ }
+
+ /* Setup the VIA interrupts */
+ request_resource(&ioport_resource, &pic1_io_resource);
+ request_resource(&ioport_resource, &pic2_io_resource);
+ setup_irq(2, &via_irq2);
+
+ /* This may be too simple.. FIX it later */
+ VIA_PORT_WRITE(0x20, 0x10);
+ VIA_PORT_WRITE(0x21, 0x00);
+ VIA_PORT_WRITE(0x21, 0x00);
+
+ VIA_PORT_WRITE(0xa0, 0x10);
+ VIA_PORT_WRITE(0xa1, 0x00);
+ VIA_PORT_WRITE(0xa1, 0x00);
+
+ /* Mask all cpu interrupts
+ (except IE4, we already masked those at VIA level) */
+ clear_cp0_status(ST0_IM);
+ set_cp0_status(IE_IRQ4);
+
+ cli();
+
+ set_except_vector(0, cobalt_handle_int);
}
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/pci.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- pci.c 30 Nov 2001 18:34:09 -0000 1.7
+++ pci.c 21 Apr 2002 20:56:23 -0000 1.8
@@ -1,10 +1,15 @@
/*
+ * Cobalt Qube/Raq PCI support
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Cobalt Qube specific PCI support.
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
*/
+
#include <linux/config.h>
#include <linux/types.h>
#include <linux/pci.h>
@@ -17,8 +22,6 @@
#ifdef CONFIG_PCI
-#define SELF 0
-
static void qube_expansion_slot_bist(void)
{
unsigned char ctrl;
@@ -42,7 +45,7 @@
static void qube_expansion_slot_fixup(void)
{
unsigned short pci_cmd;
- unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */
+ unsigned long ioaddr_base = 0x108000; /* It's magic, ask Doug. */
unsigned long memaddr_base = 0x12000000;
int i;
@@ -82,94 +85,62 @@
alignme = 0x400;
rval = ((*basep + (alignme - 1)) & ~(alignme - 1));
*basep = (rval + size);
- pcibios_write_config_dword(0,(0x0a<<3), regaddr, rval | aspace);
+ pcibios_write_config_dword(0, (0x0a<<3), regaddr, rval | aspace);
}
qube_expansion_slot_bist();
}
-#define DEFAULT_BMIBA 0xcc00 /* in case ROM did not init it */
-
static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
{
unsigned short cfgword;
unsigned char lt;
- unsigned int bmiba;
- int try_again = 1;
/* Enable Bus Mastering and fast back to back. */
pci_read_config_word(dev, PCI_COMMAND, &cfgword);
cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
pci_write_config_word(dev, PCI_COMMAND, cfgword);
- /* Enable interfaces. ROM only enables primary one. */
- {
-#ifdef CONFIG_BLK_DEV_COBALT_SECONDARY
- unsigned char iface_enable = 0xb;
-#else
- unsigned char iface_enable = 0xa;
-#endif
- pci_write_config_byte(dev, 0x40, iface_enable);
- }
+ /* Enable both ide interfaces. ROM only enables primary one. */
+ pci_write_config_byte(dev, 0x40, 0xb);
/* Set latency timer to reasonable value. */
pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
- if (lt < 64)
+ if(lt < 64)
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
-
- /* Get the bmiba base address. */
- do {
- pci_read_config_dword(dev, 0x20, &bmiba);
- bmiba &= 0xfff0; /* extract port base address */
- if (bmiba) {
- break;
- } else {
- printk("ide: BM-DMA base register is invalid (0x%08x)\n",bmiba);
- if (inb(DEFAULT_BMIBA) != 0xff || !try_again)
- break;
- printk("ide: setting BM-DMA base register to 0x%08x\n",DEFAULT_BMIBA);
- pci_write_config_dword(dev, 0x20, DEFAULT_BMIBA|1);
- }
- } while (try_again--);
-
- bmiba += 0x10000000;
-
- dev->resource[4].start = bmiba;
}
static void qube_raq_tulip_fixup(struct pci_dev *dev)
{
unsigned short pci_cmd;
extern int cobalt_is_raq;
- unsigned int tmp;
/* Fixup the first tulip located at device PCICONF_ETH0 */
- if (dev->devfn == PCI_DEVSHFT(COBALT_PCICONF_ETH0)) {
+ if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) {
/*
* Now tell the Ethernet device that we expect an interrupt at
* IRQ 13 and not the default 189.
*
* The IRQ of the first Tulip is different on Qube and RaQ
- * hardware except for the weird first RaQ bringup board,
*/
- if (! cobalt_is_raq) {
+ if (!cobalt_is_raq) {
/* All Qube's route this the same way. */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
- COBALT_ETHERNET_IRQ);
+ COBALT_QUBE_ETH_IRQ);
} else {
/* Setup the first Tulip on the RAQ */
-#ifndef RAQ_BOARD_1_WITH_HWHACKS
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
-#else
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 13);
-#endif
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+ COBALT_RAQ_ETH0_IRQ);
+ }
+ dev->resource[0].start = 0x100000;
+ dev->resource[0].end = 0x10007f;
+ if (dev->resource[1].start < 0x10000000) {
+ dev->resource[1].start = 0xe9ffec00;
+ dev->resource[1].end = 0xe9ffefff;
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0xe9ffec00);
}
/* Fixup the second tulip located at device PCICONF_ETH1 */
- } else if (dev->devfn == PCI_DEVSHFT(COBALT_PCICONF_ETH1)) {
- /* XXX Check for the second Tulip on the RAQ(Already got it!) */
- pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
- if(tmp == 0xffffffff || tmp == 0x00000000)
- return;
+ } else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) {
/* Enable the second Tulip device. */
pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
@@ -177,19 +148,14 @@
pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
/* Give it it's IRQ. */
- /* NOTE: RaQ board #1 has a bunch of green wires which swapped
- * the IRQ line values of Tulip 0 and Tulip 1. All other
- * boards have eth0=4,eth1=13. -DaveM
- */
-#ifndef RAQ_BOARD_1_WITH_HWHACKS
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 13);
-#else
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
-#endif
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+ COBALT_RAQ_ETH1_IRQ);
+
/* And finally, a usable I/O space allocation, right after what
* the first Tulip uses.
*/
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10101001);
+ dev->resource[0].start = 0x101000;
+ dev->resource[0].end = 0x10107f;
}
}
@@ -197,7 +163,6 @@
{
unsigned short pci_cmd;
extern int cobalt_is_raq;
- unsigned int tmp;
/*
* Tell the SCSI device that we expect an interrupt at
@@ -206,18 +171,15 @@
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ);
if (cobalt_is_raq) {
- /* Check for the SCSI on the RAQ */
- pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
- if(tmp == 0xffffffff || tmp == 0x00000000)
- return;
/* Enable the device. */
pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
- pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE);
+ pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_INVALIDATE);
pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
- /* Give it it's IRQ. */
+ /* Give it it's RAQ IRQ. */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
/* And finally, a usable I/O space allocation, right after what
@@ -252,7 +214,7 @@
/* New Galileo, assumes PCI stop line to VIA is connected. */
*((volatile unsigned int *)0xb4000c04) = 0x00004020;
} else if (galileo_id == 0x1 || galileo_id == 0x2) {
- unsigned int timeo;
+ signed int timeo;
/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
timeo = *((volatile unsigned int *)0xb4000c04);
/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
@@ -263,11 +225,8 @@
static void
qube_pcibios_fixup(struct pci_dev *dev)
{
- extern int cobalt_is_raq;
unsigned int tmp;
-
- if (! cobalt_is_raq) {
/* See if there is a device in the expansion slot, if so
* fixup IRQ, fix base addresses, and enable master +
* I/O + memory accesses in config space.
@@ -275,27 +234,17 @@
pcibios_read_config_dword(0, 0x0a<<3, PCI_VENDOR_ID, &tmp);
if(tmp != 0xffffffff && tmp != 0x00000000)
qube_expansion_slot_fixup();
- } else {
- /* And if we are a 2800 we have to setup the expansion slot
- * too.
- */
- pcibios_read_config_dword(0, 0x0a<<3, PCI_VENDOR_ID, &tmp);
- if(tmp != 0xffffffff && tmp != 0x00000000)
- qube_expansion_slot_fixup();
- }
}
struct pci_fixup pcibios_fixups[] = {
- /* TBD:: Add each device here and divvy up pcibios_fixup */
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup },
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup },
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup },
- /* Not sure about what scsi chips are available on the RAQ, put an
- entry for all */
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup },
{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup }
};
+
static __inline__ int pci_range_ck(struct pci_dev *dev)
{
if ((dev->bus->number == 0)
@@ -303,6 +252,7 @@
|| ((PCI_SLOT (dev->devfn) > 6)
&& (PCI_SLOT (dev->devfn) <= 12))))
return 0; /* OK device number */
+
return -1; /* NOT ok device number */
}
@@ -313,7 +263,9 @@
((*PCI_CFG_CTRL) = (0x80000000 | (PCI_SLOT ((dev)->devfn) << 11) | \
(PCI_FUNC ((dev)->devfn) << 8) | (where)))
-static int qube_pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
+static int qube_pci_read_config_dword (struct pci_dev *dev,
+ int where,
+ u32 *val)
{
if (where & 0x3)
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -326,7 +278,9 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
+static int qube_pci_read_config_word (struct pci_dev *dev,
+ int where,
+ u16 *val)
{
if (where & 0x1)
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -339,7 +293,9 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
+static int qube_pci_read_config_byte (struct pci_dev *dev,
+ int where,
+ u8 *val)
{
if (pci_range_ck (dev)) {
*val = 0xff;
@@ -350,9 +306,11 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
+static int qube_pci_write_config_dword (struct pci_dev *dev,
+ int where,
+ u32 val)
{
- if (where & 0x3)
+ if(where & 0x3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (pci_range_ck (dev))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -361,7 +319,10 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
+static int
+qube_pci_write_config_word (struct pci_dev *dev,
+ int where,
+ u16 val)
{
unsigned long tmp;
@@ -377,7 +338,10 @@
return PCIBIOS_SUCCESSFUL;
}
-static int qube_pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
+static int
+qube_pci_write_config_byte (struct pci_dev *dev,
+ int where,
+ u8 val)
{
unsigned long tmp;
@@ -391,6 +355,7 @@
return PCIBIOS_SUCCESSFUL;
}
+
struct pci_ops qube_pci_ops = {
qube_pci_read_config_byte,
qube_pci_read_config_word,
@@ -405,7 +370,10 @@
printk("PCI: Probing PCI hardware\n");
ioport_resource.start = 0x00000000;
- ioport_resource.end = 0x1cffffff;
+ ioport_resource.end = 0x0fffffff;
+
+ iomem_resource.start = 0x01000000;
+ iomem_resource.end = 0xffffffff;
pci_scan_bus(0, &qube_pci_ops, NULL);
}
@@ -423,28 +391,32 @@
pci_read_config_word(dev, PCI_STATUS, &status);
printk("PCI: Enabling device %s (%04x %04x)\n", dev->slot_name, cmd, status);
/* We'll sort this out when we know it isn't enabled ;) */
- return 0; /* pcibios_enable_resources */
+
+ return 0;
}
-void pcibios_align_resource(void *data, struct resource *res,unsigned long size)
+void pcibios_align_resource(void *data, struct resource *res,
+ unsigned long size)
{
- panic("Uhhoh called pcibios_align_resource");
+ panic("Uhhoh called pcibios_align_resource\n");
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
- panic("Uhhoh called pcibios_update_resource");
+
+ panic("Uhhoh called pcibios_update_resource\n");
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
- /* We don't appear to have sub-busses to fixup here */
+ /* We don't have sub-busses to fixup here */
}
-unsigned __init int pcibios_assign_all_busses(void)
+unsigned int __init pcibios_assign_all_busses(void)
{
return 1;
}
+
#endif /* CONFIG_PCI */
Index: promcon.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/promcon.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- promcon.c 2 Jul 2001 18:03:24 -0000 1.1
+++ promcon.c 21 Apr 2002 20:56:23 -0000 1.2
@@ -1,3 +1,15 @@
+/*
+ * PROM console for Cobalt Raq2
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
+ */
+
#include <linux/init.h>
#include <linux/console.h>
#include <linux/kdev_t.h>
@@ -8,21 +20,20 @@
#include <asm/serial.h>
#include <asm/io.h>
-static unsigned long port = 0x1c800000;
+static unsigned long port = 0xc800000;
static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
{
char lsr;
- do { lsr = inb(ioaddr + UART_LSR);
+ do {
+ lsr = inb(ioaddr + UART_LSR);
} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
outb(ch, ioaddr + UART_TX);
}
static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
{
- char lsr;
-
while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
udelay(1);
return inb(ioaddr + UART_RX);
@@ -36,13 +47,16 @@
ier = inb(port + UART_IER);
outb(0x00, port + UART_IER);
for (i=0; i < count; i++, s++) {
+
if(*s == '\n')
ns16550_cons_put_char('\r', port);
ns16550_cons_put_char(*s, port);
}
- do { lsr = inb(port + UART_LSR);
+ do {
+ lsr = inb(port + UART_LSR);
} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
+
outb(ier, port + UART_IER);
}
@@ -56,7 +70,8 @@
ns16550_cons_put_char(kgdb_char, port);
}
-static kdev_t ns16550_console_dev(struct console *c)
+static kdev_t
+ns16550_console_dev(struct console *c)
{
return MKDEV(TTY_MAJOR, 64 + c->index);
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/setup.c,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- setup.c 2 Jan 2002 19:12:16 -0000 1.19
+++ setup.c 21 Apr 2002 20:56:23 -0000 1.20
@@ -1,18 +1,19 @@
/*
- * Setup pointers to hardware dependand routines.
+ * Setup pointers to hardware dependent routines.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ld...@ag...)
+ *
*/
+
#include <linux/config.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
-#include <linux/timex.h>
+#include <linux/mc146818rtc.h>
#include <linux/init.h>
#include <linux/ide.h>
@@ -23,23 +24,25 @@
#include <asm/cobalt/cobalt.h>
#include <asm/pci.h>
#include <asm/processor.h>
-#include <asm/ptrace.h>
#include <asm/reboot.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
extern void cobalt_machine_power_off(void);
-
extern void rtc_dallas_init(unsigned long base);
+extern struct ide_ops std_ide_ops;
-extern struct ide_ops cobalt_ide_ops;
-
-char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 root=/dev/hda1"};
+char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 root=/dev/hda1" };
void __init bus_error_init(void)
{
}
+const char *get_system_type(void)
+{
+ return "MIPS Cobalt";
+}
+
#define GALILEO_T0_VAL 0xb4000850
#define GALILEO_TIMER_CTRL 0xb4000864
#define GALILEO_CPU_MASK 0xb4000c1c
@@ -47,23 +50,16 @@
#define GALILEO_ENTC0 0x01
#define GALILEO_SELTC0 0x02
-static void __init cobalt_calibrate_timer(void)
+static void __init cobalt_timer_setup(struct irqaction *irq)
{
+ /* Load timer value for 150 Hz */
volatile unsigned long *timer_reg = (volatile unsigned long *)GALILEO_T0_VAL;
- /* Default to 150MHZ, since this is what we are shipping. */
*timer_reg = 500000;
-}
-
-static void __init cobalt_timer_setup(struct irqaction *irq)
-{
- /* Load timer value for 150 Hz */
- cobalt_calibrate_timer();
+ /* Register our timer interrupt */
setup_irq(0, irq);
- change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
-
/* Enable timer ints */
*((volatile unsigned long *) GALILEO_TIMER_CTRL) =
(unsigned long) (GALILEO_ENTC0 | GALILEO_SELTC0);
@@ -73,8 +69,6 @@
static void __init cobalt_time_init(void)
{
- //mips_counter_frequency = 83000000;
-
/* we have ds1396 RTC chip */
rtc_dallas_init(VIA_CMOS_ADDR);
@@ -94,8 +88,6 @@
/*
* IO/MEM resources.
*/
- set_io_port_base(COBALT_LOCAL_IO_SPACE);
- isa_slot_offset = 0xb0000000;
#ifdef CONFIG_NEW_PCI
ioport_resource.start = 0x10000000;
@@ -114,8 +106,16 @@
board_timer_setup = cobalt_timer_setup;
#ifdef CONFIG_BLK_DEV_IDE
- ide_ops = &cobalt_ide_ops;
+ ide_ops = &std_ide_ops;
#endif
+ set_io_port_base(0xb0000000);
+
+ /*
+ * This is a prom style console. We just poke at the
+ * UART to make it talk.
+ * Only use this console if you really screw up and can't
+ * get to the stage of setting up a real serial console.
+ */
/*ns16550_setup_console();*/
/* We have to do this early, here, before the value could
@@ -127,14 +127,9 @@
&& cobalt_serial_type == 0x1);
}
-const char *get_system_type(void)
-{
- return "Cobalt"; /* But which exactly? */
-}
-
-/* prom_init() is called just after the cpu type is determined, from
- init_arch(). */
-void __init prom_init(int argc, char **arg)
+/* Prom init. We read our one and only communication with the
+ firmware. Grab the amount of installed memory */
+void __init prom_init(int argc)
{
mips_machgroup = MACH_GROUP_COBALT;
@@ -143,5 +138,5 @@
void __init prom_free_prom_memory(void)
{
- /* Something to do here?? */
+ /* Nothing to do! */
}
|
|
From: Paul M. <le...@us...> - 2002-04-21 20:56:26
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv19938/arch/mips
Modified Files:
config.in
Log Message:
Make cobalt work again. (Hopefully the end of OSS syncing for today.)
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.93
retrieving revision 1.94
diff -u -d -r1.93 -r1.94
--- config.in 21 Apr 2002 18:03:11 -0000 1.93
+++ config.in 21 Apr 2002 20:56:23 -0000 1.94
@@ -343,8 +343,13 @@
define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_I8259 y
- define_bool CONFIG_NEW_PCI y
- define_bool CONFIG_PCI_AUTO y
+ #
+ # FIXME: Currently only old-style PCI works.
+ # Leave these commented out until new-style
+ # is fixed.
+ #
+ # define_bool CONFIG_NEW_PCI y
+ # define_bool CONFIG_PCI_AUTO y
fi
if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
define_bool CONFIG_PCI y
|
|
From: Paul M. <le...@us...> - 2002-04-21 20:34:35
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv13729 Modified Files: pgtable.h Log Message: Yet more OSS syncing.. Index: pgtable.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgtable.h,v retrieving revision 1.16 retrieving revision 1.17 diff -u -d -r1.16 -r1.17 --- pgtable.h 23 Mar 2002 02:36:09 -0000 1.16 +++ pgtable.h 21 Apr 2002 20:34:31 -0000 1.17 @@ -117,87 +117,7 @@ # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) #endif -/* Note that we shift the lower 32bits of each EntryLo[01] entry - * 6 bits to the left. That way we can convert the PFN into the - * physical address by a single 'and' operation and gain 6 additional - * bits for storing information which isn't present in a normal - * MIPS page table. - * - * Similar to the Alpha port, we need to keep track of the ref - * and mod bits in software. We have a software "yeah you can read - * from this page" bit, and a hardware one which actually lets the - * process read from the page. On the same token we have a software - * writable bit and the real hardware one which actually lets the - * process write to the page, this keeps a mod bit via the hardware - * dirty bit. - * - * Certain revisions of the R4000 and R5000 have a bug where if a - * certain sequence occurs in the last 3 instructions of an executable - * page, and the following page is not mapped, the cpu can do - * unpredictable things. The code (when it is written) to deal with - * this problem will be in the update_mmu_cache() code for the r4k. - */ -#define _PAGE_PRESENT (1<<0) /* implemented in software */ -#define _PAGE_READ (1<<1) /* implemented in software */ -#define _PAGE_WRITE (1<<2) /* implemented in software */ -#define _PAGE_ACCESSED (1<<3) /* implemented in software */ -#define _PAGE_MODIFIED (1<<4) /* implemented in software */ - -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - -#define _PAGE_GLOBAL (1<<8) -#define _PAGE_VALID (1<<9) -#define _PAGE_SILENT_READ (1<<9) /* synonym */ -#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<10) -#define _CACHE_UNCACHED (1<<11) /* R4[0246]00 */ -#define _CACHE_MASK (1<<11) -#define _CACHE_CACHABLE_NONCOHERENT 0 - -#else -#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ -#define _PAGE_GLOBAL (1<<6) -#define _PAGE_VALID (1<<7) -#define _PAGE_SILENT_READ (1<<7) /* synonym */ -#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<8) -#define _CACHE_MASK (7<<9) - -#if defined(CONFIG_CPU_SB1) - -/* No penalty for being coherent on the SB1, so just - use it for "noncoherent" spaces, too. Shouldn't hurt. */ - -#define _CACHE_UNCACHED (2<<9) -#define _CACHE_CACHABLE_COW (5<<9) -#define _CACHE_CACHABLE_NONCOHERENT (5<<9) - -#else - -#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */ -#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */ -#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */ -#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */ -#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */ -#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */ - -#endif -#endif - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) - -#ifdef CONFIG_MIPS_UNCACHED -#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif CONFIG_CPU_SB1 -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW -#else -#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT -#endif +#include <asm/pgtable-bits.h> #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ |
|
From: Paul M. <le...@us...> - 2002-04-21 20:19:20
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv9602/include/asm-mips
Modified Files:
io.h
Log Message:
More syncing..
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.20
retrieving revision 1.21
diff -u -d -r1.20 -r1.21
--- io.h 24 Mar 2002 00:01:51 -0000 1.20
+++ io.h 21 Apr 2002 20:19:17 -0000 1.21
@@ -15,6 +15,7 @@
#include <linux/pagemap.h>
#include <linux/types.h>
#include <asm/addrspace.h>
+#include <asm/pgtable-bits.h>
#include <asm/byteorder.h>
/*
@@ -134,25 +135,14 @@
extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
-static inline void *ioremap(phys_t offset, unsigned long size)
-{
- return __ioremap(offset, size, _CACHE_UNCACHED);
-}
-
-static inline void *ioremap_nocache(phys_t offset, unsigned long size)
-{
- return __ioremap(offset, size, _CACHE_UNCACHED);
-}
-
-static inline void *ioremap_cacheable_cow(phys_t offset, unsigned long size)
-{
- return __ioremap(offset, size, _CACHE_CACHABLE_COW);
-}
-
-static inline void *ioremap_uncached_accelerated(phys_t offset, unsigned long size)
-{
- return __ioremap(offset, size, _CACHE_UNCACHED_ACCELERATED);
-}
+#define ioremap(offset, size) \
+ __ioremap((offset), (size), _CACHE_UNCACHED)
+#define ioremap_nocache(offset, size) \
+ __ioremap((offset), (size), _CACHE_UNCACHED)
+#define ioremap_cacheable_cow(offset, size) \
+ __ioremap((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size) \
+ __ioremap((offset), (size), _CACHE_UNCACHED_ACCELERATED)
extern void iounmap(void *addr);
|
|
From: Paul M. <le...@us...> - 2002-04-21 20:06:23
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64 In directory usw-pr-cvs1:/tmp/cvs-serv5941/include/asm-mips64 Modified Files: asm.h paccess.h smp.h Log Message: Yet more OSS syncing.. Index: asm.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/asm.h,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- asm.h 28 Jan 2002 20:32:05 -0000 1.8 +++ asm.h 21 Apr 2002 20:06:20 -0000 1.9 @@ -115,8 +115,8 @@ #define TTABLE(string) \ .pushsection .text; \ .word 1f; \ - .previous; \ - .data; \ + .popsection \ + .pushsection .data; \ 1: .asciz string; \ .popsection Index: paccess.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/paccess.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- paccess.h 2 Jan 2002 19:12:18 -0000 1.1 +++ paccess.h 21 Apr 2002 20:06:20 -0000 1.2 @@ -15,9 +15,6 @@ #include <linux/errno.h> -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - #define put_dbe(x,ptr) __put_dbe((x),(ptr),sizeof(*(ptr))) #define get_dbe(x,ptr) __get_dbe((x),(ptr),sizeof(*(ptr))) @@ -90,10 +87,5 @@ :"r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT)); }) extern void __put_dbe_unknown(void); - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -extern unsigned long search_dbe_table(unsigned long addr); #endif /* _ASM_PACCESS_H */ Index: smp.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/smp.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- smp.h 17 Dec 2001 18:46:02 -0000 1.6 +++ smp.h 21 Apr 2002 20:06:20 -0000 1.7 @@ -6,7 +6,6 @@ * Copyright (C) 2000 - 2001 by Kanoj Sarcar (ka...@sg...) * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc. */ - #ifndef __ASM_SMP_H #define __ASM_SMP_H @@ -42,7 +41,7 @@ typedef unsigned long cpumask_t; #define CPUMASK_CLRALL(p) (p) = 0 -#define CPUMASK_SETB(p, bit) (p) |= 1 << (bit) +#define CPUMASK_SETB(p, bit) (p) |= 1UL << (bit) #define CPUMASK_CLRB(p, bit) (p) &= ~(1ULL << (bit)) #define CPUMASK_TSTB(p, bit) ((p) & (1ULL << (bit))) |
|
From: Paul M. <le...@us...> - 2002-04-21 20:06:23
|
Update of /cvsroot/linux-mips/linux/include/linux In directory usw-pr-cvs1:/tmp/cvs-serv5941/include/linux Modified Files: netdevice.h pci_ids.h Log Message: Yet more OSS syncing.. Index: netdevice.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/linux/netdevice.h,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- netdevice.h 26 Feb 2002 19:03:33 -0000 1.8 +++ netdevice.h 21 Apr 2002 20:06:20 -0000 1.9 @@ -39,11 +39,6 @@ #include <net/profile.h> #endif -#ifdef CONFIG_COBALT_27 -typedef int (*linkcheck_func_t)(void *cookie); -extern int lcd_register_linkcheck_func(int iface_num, void *func, void *cookie); -#endif /* CONFIG_COBALT_27 */ - struct divert_blk; #define HAVE_ALLOC_NETDEV /* feature macro: alloc_xxxdev Index: pci_ids.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/linux/pci_ids.h,v retrieving revision 1.15 retrieving revision 1.16 diff -u -d -r1.15 -r1.16 --- pci_ids.h 15 Jan 2002 00:34:07 -0000 1.15 +++ pci_ids.h 21 Apr 2002 20:06:20 -0000 1.16 @@ -355,6 +355,7 @@ #define PCI_VENDOR_ID_WD 0x101c #define PCI_DEVICE_ID_WD_7197 0x3296 +#define PCI_DEVICE_ID_WD_90C 0xc24a #define PCI_VENDOR_ID_AMI 0x101e #define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 @@ -651,6 +652,12 @@ #define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 #define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 +#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 +#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025 +#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d #define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 #define PCI_VENDOR_ID_YAMAHA 0x1073 @@ -860,11 +867,17 @@ #define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 #define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 #define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 #define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 #define PCI_VENDOR_ID_IMS 0x10e0 #define PCI_DEVICE_ID_IMS_8849 0x8849 @@ -1124,6 +1137,8 @@ #define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 #define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 #define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 +#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 #define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 #define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 #define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 @@ -1500,6 +1515,7 @@ #define PCI_VENDOR_ID_AFAVLAB 0x14db #define PCI_DEVICE_ID_AFAVLAB_TK9902 0x2120 +#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 #define PCI_VENDOR_ID_BROADCOM 0x14e4 #define PCI_DEVICE_ID_TIGON3_5700 0x1644 |
|
From: Paul M. <le...@us...> - 2002-04-21 20:06:23
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/dec
In directory usw-pr-cvs1:/tmp/cvs-serv5941/include/asm-mips/dec
Modified Files:
interrupts.h ioasic.h
Log Message:
Yet more OSS syncing..
Index: interrupts.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/dec/interrupts.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- interrupts.h 26 Nov 2001 19:31:47 -0000 1.4
+++ interrupts.h 21 Apr 2002 20:06:20 -0000 1.5
@@ -8,6 +8,7 @@
*
* Copyright (C) 1997 by Paul M. Antoine.
* reworked 1998 by Harald Koerfgen.
+ * Copyright (C) 2001, 2002 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_INTERRUPTS_H
@@ -15,77 +16,110 @@
#include <asm/mipsregs.h>
-/*
- * DECstation Interrupts
- */
/*
- * This list reflects the priority of the Interrupts.
- * Exception: on kmins we have to handle Memory Error
- * Interrupts before the TC Interrupts.
+ * The list of possible system devices which provide an
+ * interrupt. Not all devices exist on a given system.
*/
-#define CLOCK 0
-#define SCSI_DMA_INT 1
-#define SCSI_INT 2
-#define ETHER 3
-#define SERIAL 4
-#define TC0 5
-#define TC1 6
-#define TC2 7
-#define MEMORY 8
-#define HALT 9
+#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
-#define NR_INTS 10
+/* Ordinary interrupts */
+#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
+#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
+#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */
+#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */
+#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */
+#define DEC_IRQ_FPU 6 /* R3k FPU */
+#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
+#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */
+#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */
+#define DEC_IRQ_MEMORY 10 /* memory, I/O bus write errors */
+#define DEC_IRQ_PSU 11 /* power supply unit warning */
+#define DEC_IRQ_RTC 12 /* DS1287 RTC */
+#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
+#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
+#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */
+#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */
+#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */
+#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */
+#define DEC_IRQ_TIMER 19 /* ARC periodic timer */
+#define DEC_IRQ_VIDEO 20 /* framebuffer */
+
+/* I/O ASIC DMA interrupts */
+#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */
+#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */
+#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */
+#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */
+#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */
+#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */
+#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */
+#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */
+#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */
+#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
+#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */
+#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */
+#define DEC_IRQ_SCC0B_RXERR 33 /* SCC0B (ACCESS.bus) receive overrun */
+#define DEC_IRQ_SCC0B_RXDMA 34 /* SCC0B receive half page */
+#define DEC_IRQ_SCC0B_TXERR 35 /* SCC0B xmit memory read/overrun */
+#define DEC_IRQ_SCC0B_TXDMA 36 /* SCC0B transmit page end */
+#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */
+#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */
+#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */
+#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */
+
+/* TC5 & TC6 are virtual slots for KN02's onboard devices */
+#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */
+#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */
+
+#define DEC_NR_INTS 41
+
+
+/* Largest of cpu mask_nr tables. */
+#define DEC_MAX_CPU_INTS 6
+/* Largest of asic mask_nr tables. */
+#define DEC_MAX_ASIC_INTS 9
-/*
- * The FPU is special. It must always be handled first.
- * Since it bypasses the regular IRQ handler we define
- * the line it uses here. All DECstations use the same
- * one.
- */
-#define DEC_IE_FPU IE_IRQ5
-#ifndef __ASSEMBLY__
/*
- * Data structure to hide the differences between the DECstation Interrupts
- *
- * If asic_mask == NULL, the interrupt is directly handled by the CPU.
- * Otherwise this Interrupt is handled the IRQ Controller.
+ * CPU interrupt bits common to all systems.
*/
+#define DEC_CPU_INR_FPU 7 /* R3k FPU */
+#define DEC_CPU_INR_SW1 1 /* software #1 */
+#define DEC_CPU_INR_SW0 0 /* software #0 */
-typedef struct
-{
- unsigned int cpu_mask; /* checking and enabling interrupts in CP0 */
- unsigned int iemask; /* enabling interrupts in IRQ Controller */
-} decint_t;
+#define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */
-extern volatile unsigned int *isr;
- /* address of the interrupt status register */
-extern volatile unsigned int *imr;
- /* address of the interrupt mask register */
-extern decint_t dec_interrupt[NR_INTS];
+#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
+#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
+#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
+
+
+#ifndef __ASSEMBLY__
/*
- * Interrupt table structure to hide differences between different
- * systems such.
+ * Interrupt table structures to hide differences between systems.
*/
-extern void *cpu_ivec_tbl[8];
-extern long cpu_mask_tbl[8];
-extern long cpu_irq_nr[8];
-extern long asic_irq_nr[32];
-extern long asic_mask_tbl[32];
+typedef union { int i; void *p; } int_ptr;
+extern int dec_interrupt[DEC_NR_INTS];
+extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
+extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
+extern int cpu_fpu_mask;
+
/*
* Common interrupt routine prototypes for all DECStations
*/
-extern void dec_intr_unimplemented(void);
-
extern void kn02_io_int(void);
extern void kn02xa_io_int(void);
extern void kn03_io_int(void);
+extern void asic_dma_int(void);
+extern void asic_all_int(void);
+extern void kn02_all_int(void);
+extern void cpu_all_int(void);
+extern void dec_intr_unimplemented(void);
extern void asic_intr_unimplemented(void);
-#endif
-#endif
+#endif /* __ASSEMBLY__ */
+#endif
Index: ioasic.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/dec/ioasic.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ioasic.h 31 Oct 2001 18:26:52 -0000 1.2
+++ ioasic.h 21 Apr 2002 20:06:20 -0000 1.3
@@ -1,24 +1,33 @@
/*
* linux/asm-mips/dec/ioasic.h
*
- * Copyright (C) 2000 Maciej W. Rozycki
- *
* DEC I/O ASIC access operations.
+ *
+ * Copyright (C) 2000, 2002 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_DEC_IOASIC_H
#define __ASM_DEC_IOASIC_H
-extern volatile unsigned int *ioasic_base;
+#include <linux/types.h>
-static inline void ioasic_write(unsigned int reg, unsigned int v)
+extern volatile u32 *ioasic_base;
+
+static inline void ioasic_write(unsigned int reg, u32 v)
{
ioasic_base[reg / 4] = v;
}
-static inline unsigned int ioasic_read(unsigned int reg)
+static inline u32 ioasic_read(unsigned int reg)
{
return ioasic_base[reg / 4];
}
+
+extern void init_ioasic_irqs(int base);
#endif /* __ASM_DEC_IOASIC_H */
|
|
From: Paul M. <le...@us...> - 2002-04-21 20:06:22
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv5941/include/asm-mips
Modified Files:
ptrace.h serial.h stackframe.h
Log Message:
Yet more OSS syncing..
Index: ptrace.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/ptrace.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- ptrace.h 12 Feb 2002 18:00:14 -0000 1.3
+++ ptrace.h 21 Apr 2002 20:06:20 -0000 1.4
@@ -48,6 +48,32 @@
unsigned long cp0_cause;
};
+#define __str2(x) #x
+#define __str(x) __str2(x)
+
+#define save_static_function(symbol) \
+__asm__ ( \
+ ".globl\t" #symbol "\n\t" \
+ ".align\t2\n\t" \
+ ".type\t" #symbol ", @function\n\t" \
+ ".ent\t" #symbol ", 0\n" \
+ #symbol":\n\t" \
+ ".frame\t$29, 0, $31\n\t" \
+ "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \
+ "sw\t$17,"__str(PT_R17)"($29)\n\t" \
+ "sw\t$18,"__str(PT_R18)"($29)\n\t" \
+ "sw\t$19,"__str(PT_R19)"($29)\n\t" \
+ "sw\t$20,"__str(PT_R20)"($29)\n\t" \
+ "sw\t$21,"__str(PT_R21)"($29)\n\t" \
+ "sw\t$22,"__str(PT_R22)"($29)\n\t" \
+ "sw\t$23,"__str(PT_R23)"($29)\n\t" \
+ "sw\t$30,"__str(PT_R30)"($29)\n\t" \
+ ".end\t" #symbol "\n\t" \
+ ".size\t" #symbol",. - " #symbol)
+
+/* Used in declaration of save_static functions. */
+#define static_unused static __attribute__((unused))
+
#endif /* !(_LANGUAGE_ASSEMBLY) */
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/serial.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- serial.h 19 Jan 2002 01:35:17 -0000 1.11
+++ serial.h 21 Apr 2002 20:06:20 -0000 1.12
@@ -84,11 +84,11 @@
#define ATLAS_SERIAL_PORT_DEFNS
#endif
-#ifdef CONFIG_COBALT_MICRO_SERVER
+#ifdef CONFIG_MIPS_COBALT
#define COBALT_BASE_BAUD (18432000 / 16)
#define COBALT_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
- { 0, COBALT_BASE_BAUD, 0x1c800000, 7, STD_COM_FLAGS }, /* ttyS0 */
+ { 0, COBALT_BASE_BAUD, 0xc800000, 7, STD_COM_FLAGS }, /* ttyS0 */
#else
#define COBALT_SERIAL_PORT_DEFNS
#endif
Index: stackframe.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/stackframe.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- stackframe.h 24 Oct 2001 23:32:54 -0000 1.3
+++ stackframe.h 21 Apr 2002 20:06:20 -0000 1.4
@@ -9,12 +9,12 @@
#ifndef __ASM_STACKFRAME_H
#define __ASM_STACKFRAME_H
+#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>
#include <asm/asm.h>
#include <asm/offset.h>
-#include <linux/config.h>
#define SAVE_AT \
.set push; \
@@ -47,33 +47,6 @@
sw $22, PT_R22(sp); \
sw $23, PT_R23(sp); \
sw $30, PT_R30(sp)
-
-#define __str2(x) #x
-#define __str(x) __str2(x)
-
-#define save_static_function(symbol) \
-__asm__ ( \
- ".globl\t" #symbol "\n\t" \
- ".align\t2\n\t" \
- ".type\t" #symbol ", @function\n\t" \
- ".ent\t" #symbol ", 0\n" \
- #symbol":\n\t" \
- ".frame\t$29, 0, $31\n\t" \
- "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \
- "sw\t$17,"__str(PT_R17)"($29)\n\t" \
- "sw\t$18,"__str(PT_R18)"($29)\n\t" \
- "sw\t$19,"__str(PT_R19)"($29)\n\t" \
- "sw\t$20,"__str(PT_R20)"($29)\n\t" \
- "sw\t$21,"__str(PT_R21)"($29)\n\t" \
- "sw\t$22,"__str(PT_R22)"($29)\n\t" \
- "sw\t$23,"__str(PT_R23)"($29)\n\t" \
- "sw\t$30,"__str(PT_R30)"($29)\n\t" \
- ".end\t" #symbol "\n\t" \
- ".size\t" #symbol",. - " #symbol)
-
-/* Used in declaration of save_static functions. */
-#define static_unused static __attribute__((unused))
-
#ifdef CONFIG_SMP
# define GET_SAVED_SP \
|
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