Menu
▾
▴
linux-mips-commits — CVS Commit Patches
You can subscribe to this list here.
| 2001 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
(165) |
Sep
(240) |
Oct
(424) |
Nov
(526) |
Dec
(293) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2002 |
Jan
(242) |
Feb
(149) |
Mar
(143) |
Apr
(143) |
May
(76) |
Jun
(59) |
Jul
(20) |
Aug
(2) |
Sep
(49) |
Oct
(1) |
Nov
(4) |
Dec
|
| 2003 |
Jan
(1) |
Feb
|
Mar
|
Apr
(1) |
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2004 |
Jan
|
Feb
|
Mar
|
Apr
(2) |
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
|
Nov
|
Dec
|
| 2008 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
(3) |
Nov
|
Dec
|
| 2009 |
Jan
|
Feb
|
Mar
|
Apr
|
May
(1) |
Jun
(72) |
Jul
(36) |
Aug
(9) |
Sep
(16) |
Oct
(23) |
Nov
(9) |
Dec
(3) |
| 2010 |
Jan
|
Feb
(1) |
Mar
(35) |
Apr
(44) |
May
(56) |
Jun
(71) |
Jul
(41) |
Aug
(41) |
Sep
(22) |
Oct
(3) |
Nov
(1) |
Dec
(1) |
| 2011 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
(1) |
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2012 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
(1) |
| 2013 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
|
Nov
|
Dec
|
| 2014 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
| 2015 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
(1) |
Sep
|
Oct
(1) |
Nov
(1) |
Dec
|
| 2016 |
Jan
|
Feb
|
Mar
|
Apr
|
May
(1) |
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
(1) |
Dec
|
| 2017 |
Jan
|
Feb
|
Mar
(1) |
Apr
(1) |
May
(1) |
Jun
|
Jul
(1) |
Aug
|
Sep
(1) |
Oct
|
Nov
|
Dec
|
| 2021 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
(1) |
Aug
(1) |
Sep
(25) |
Oct
(105) |
Nov
(15) |
Dec
|
| 2025 |
Jan
(1) |
Feb
|
Mar
|
Apr
|
May
(4) |
Jun
|
Jul
(1) |
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev64120 In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/galileo-boards/ev64120 Modified Files: setup.c Log Message: Sync to 2.4.7 Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev64120/setup.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** setup.c 2001/06/22 02:29:31 1.1.1.1 --- setup.c 2001/08/25 02:19:27 1.2 *************** *** 56,60 **** extern struct rtc_ops no_rtc_ops; - struct rtc_ops *rtc_ops; /* These functions are used for rebooting or halting the machine*/ --- 56,59 ---- *************** *** 85,89 **** } ! void (*board_time_init) (struct irqaction * irq); static unsigned char galileo_rtc_read_data(unsigned long addr) --- 84,88 ---- } ! extern void (*board_time_init) (struct irqaction * irq); static unsigned char galileo_rtc_read_data(unsigned long addr) |
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100
In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/galileo-boards/ev96100
Modified Files:
init.c irq.c setup.c time.c
Log Message:
Sync to 2.4.7
Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/init.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** init.c 2001/07/06 01:25:33 1.2
--- init.c 2001/08/25 02:19:27 1.3
***************
*** 44,52 ****
- int prom_argc;
- char **prom_argv, **prom_envp;
- char arcs_cmdline[COMMAND_LINE_SIZE];
-
/* Environment variable */
typedef struct {
char *name;
--- 44,49 ----
/* Environment variable */
+
typedef struct {
char *name;
***************
*** 54,86 ****
} t_env_var;
int init_debug = 0;
- char * __init prom_getcmdline(void)
- {
- return &(arcs_cmdline[0]);
- }
-
- void __init prom_init_cmdline(void)
- {
- char *cp;
- int actr;
-
- actr = 1; /* Always ignore argv[0] */
-
- cp = &(arcs_cmdline[0]);
- while(actr < prom_argc) {
- strcpy(cp, prom_argv[actr]);
- cp += strlen(prom_argv[actr]);
- *cp++ = ' ';
- actr++;
- }
- if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
- --cp;
- *cp = '\0';
- }
-
- void prom_free_prom_memory (void) {};
-
char *prom_getenv(char *envname)
{
--- 51,59 ----
} t_env_var;
+ int prom_argc;
+ char **prom_argv, **prom_envp;
int init_debug = 0;
char *prom_getenv(char *envname)
{
***************
*** 150,172 ****
}
- unsigned long __init prom_get_memsize(void)
- {
- char *memsize_str;
- unsigned int memsize;
-
- memsize_str = prom_getenv("memsize");
- if (!memsize_str) {
- memsize = 32; /* set to 32 MB */
- } else {
- #ifdef DEBUG
- printk("prom_memsize: %s\n", memsize_str);
- #endif
- memsize = simple_strtol(memsize_str, NULL, 0);
- }
- return memsize;
- }
void __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
prom_argc = argc;
prom_argv = argv;
--- 123,132 ----
}
void __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
+ volatile unsigned char *uart;
+ char ppbuf[8];
+
prom_argc = argc;
prom_argv = argv;
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** irq.c 2001/08/22 18:18:13 1.4
--- irq.c 2001/08/25 02:19:27 1.5
***************
*** 65,69 ****
extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
extern asmlinkage void ev96100IRQ(void);
- irq_cpustat_t irq_stat [NR_CPUS];
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
--- 65,68 ----
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** setup.c 2001/07/06 01:25:33 1.2
--- setup.c 2001/08/25 02:19:27 1.3
***************
*** 71,79 ****
extern struct rtc_ops no_rtc_ops;
extern struct resource ioport_resource;
- extern char *prom_getenv(char *envname);
! void rm7000_wbflush(void)
{
! __asm__ __volatile__ ("sync");
}
--- 71,78 ----
extern struct rtc_ops no_rtc_ops;
extern struct resource ioport_resource;
! static void rm7000_wbflush(void)
{
! __asm__ __volatile__ ("sync");
}
***************
*** 89,92 ****
--- 88,92 ----
char *argptr;
+ clear_cp0_status(ST0_FR);
__wbflush = rm7000_wbflush;
***************
*** 169,173 ****
}
#endif
-
board_time_init = ev96100_time_init;
--- 169,172 ----
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/galileo-boards/ev96100/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** time.c 2001/08/22 00:39:54 1.3
--- time.c 2001/08/25 02:19:27 1.4
***************
*** 119,123 ****
/* FIX ME */
! set_cp0_status(IE_IRQ5);
}
--- 119,123 ----
/* FIX ME */
! change_cp0_status(ST0_IM, IE_IRQ5);
}
***************
*** 261,268 ****
do {
- count = read_32bit_cp0_register(CP0_COUNT);
- timerhi += (count < timerlo); /* Wrap around */
- timerlo = count;
-
kstat.irqs[0][irq]++;
do_timer(regs);
--- 261,264 ----
|
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/au1000/common
Modified Files:
Makefile irq.c prom.c time.c
Log Message:
Sync to 2.4.7
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Makefile 2001/08/17 22:53:26 1.3
--- Makefile 2001/08/25 02:19:27 1.4
***************
*** 25,28 ****
--- 25,32 ----
obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
+ obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
+
+ ramdisk.o:
+ mkramobj ramdisk ramdisk.o
include $(TOPDIR)/Rules.make
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** irq.c 2001/08/17 22:53:26 1.3
--- irq.c 2001/08/25 02:19:27 1.4
***************
*** 73,78 ****
extern asmlinkage void au1000_IRQ(void);
extern void set_debug_traps(void);
! irq_cpustat_t irq_stat [NR_CPUS];
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
--- 73,81 ----
extern asmlinkage void au1000_IRQ(void);
+
extern void set_debug_traps(void);
! extern irq_cpustat_t irq_stat [];
! extern irq_desc_t irq_desc[NR_IRQS];
!
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
***************
*** 119,122 ****
--- 122,135 ----
+ static void disable_cpu_irq_input(unsigned int irq_nr)
+ {
+ unsigned long flags;
+
+ save_and_cli(flags);
+ mask_cpu_irq_input(irq_nr);
+ restore_flags(flags);
+ }
+
+
static void enable_cpu_irq_input(unsigned int irq_nr)
{
***************
*** 316,321 ****
local_enable_irq(irq_nr);
else
! printk("warning: end_irq %d did not enable (%x)\n",
! irq_nr, irq_desc[irq_nr].status);
}
--- 329,333 ----
local_enable_irq(irq_nr);
else
! printk("warning: end_irq %d did not enable\n", irq_nr);
}
***************
*** 472,479 ****
- /*
- * Interrupt Controller 1:
- * interrupts 32 - 63
- */
void intc1_req0_irqdispatch(struct pt_regs *regs)
{
--- 484,487 ----
***************
*** 487,491 ****
for (i=0; i<32; i++) {
if ((int_request & 0x1)) {
! do_IRQ(irq+32, regs);
}
irq++;
--- 495,499 ----
for (i=0; i<32; i++) {
if ((int_request & 0x1)) {
! do_IRQ(irq, regs);
}
irq++;
***************
*** 506,510 ****
for (i=0; i<32; i++) {
if ((int_request & 0x1)) {
! do_IRQ(irq+32, regs);
}
irq++;
--- 514,518 ----
for (i=0; i<32; i++) {
if ((int_request & 0x1)) {
! do_IRQ(irq, regs);
}
irq++;
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/prom.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** prom.c 2001/08/17 22:53:26 1.2
--- prom.c 2001/08/25 02:19:27 1.3
***************
*** 49,57 ****
char **prom_argv, **prom_envp;
! typedef struct
! {
! char *name;
! /* char *val; */
! }t_env_var;
--- 49,56 ----
char **prom_argv, **prom_envp;
! typedef struct {
! char *name;
! /* char *val; */
! } t_env_var;
***************
*** 103,107 ****
}
! inline unsigned char str2hexnum(unsigned char c)
{
if(c >= '0' && c <= '9')
--- 102,106 ----
}
! static inline unsigned char str2hexnum(unsigned char c)
{
if(c >= '0' && c <= '9')
***************
*** 112,151 ****
}
! inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
! int i;
!
! for(i = 0; i < 6; i++) {
! unsigned char num;
!
! if((*str == '.') || (*str == ':'))
! str++;
! num = str2hexnum(*str++) << 4;
! num |= (str2hexnum(*str++));
! ea[i] = num;
! }
}
-
- int get_ethernet_addr(char *ethernet_addr)
- {
- int i;
- char *ethaddr_str;
-
- ethaddr_str = prom_getenv("ethaddr");
- if (!ethaddr_str) {
- printk("ethaddr not set in boot prom\n");
- return -1;
- }
- str2eaddr(ethernet_addr, ethaddr_str);
! #if 0
! printk("get_ethernet_addr: ");
! for (i=0; i<5; i++)
! printk("%02x:", (unsigned char)*(ethernet_addr+i));
! printk("%02x\n", *(ethernet_addr+i));
! #endif
!
! return 0;
}
-
- void prom_free_prom_memory (void) {}
--- 111,120 ----
}
! int __init page_is_ram(unsigned long pagenr)
{
! return 1;
}
! void prom_free_prom_memory (void)
! {
}
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** time.c 2001/08/17 22:53:26 1.3
--- time.c 2001/08/25 02:19:27 1.4
***************
*** 1,4 ****
/*
- *
* Copyright (C) 2001 MontaVista Software, pp...@mv...
* Copied and modified Carsten Langgaard's time.c
--- 1,3 ----
***************
*** 25,31 ****
*
* Setting up the clock on the MIPS boards.
- *
*/
-
#include <linux/config.h>
#include <linux/init.h>
--- 24,28 ----
***************
*** 71,86 ****
void mips_timer_interrupt(struct pt_regs *regs)
{
! int irq = 63;
! unsigned long count;
-
if (r4k_offset == 0)
goto null;
do {
- count = read_32bit_cp0_register(CP0_COUNT);
- timerhi += (count < timerlo); /* Wrap around */
- timerlo = count;
-
kstat.irqs[0][irq]++;
do_timer(regs);
--- 68,77 ----
void mips_timer_interrupt(struct pt_regs *regs)
{
! int irq = 7;
if (r4k_offset == 0)
goto null;
do {
kstat.irqs[0][irq]++;
do_timer(regs);
***************
*** 105,111 ****
--- 96,104 ----
{
unsigned long count;
+ unsigned long cpu_pll;
unsigned long cpu_speed;
unsigned long start, end;
unsigned long counter;
+ int i;
int trim_divide = 16;
***************
*** 172,177 ****
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
! #define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
static unsigned long
--- 165,173 ----
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
! #define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff)
!
! /* Cycle counter value at the previous timer interrupt.. */
+ static unsigned int timerhi = 0, timerlo = 0;
static unsigned long
|
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477
In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/ddb5xxx/ddb5477
Modified Files:
irq.c
Log Message:
Sync to 2.4.7
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** irq.c 2001/08/23 04:20:15 1.3
--- irq.c 2001/08/25 02:19:27 1.4
***************
*** 164,165 ****
--- 164,184 ----
}
}
+
+ void (*irq_setup)(void);
+
+ void __init init_IRQ(void)
+ {
+
+ #ifdef CONFIG_REMOTE_DEBUG
+ extern void breakpoint(void);
+ extern void set_debug_traps(void);
+
+ printk("Wait for gdb client connection ...\n");
+ set_debug_traps();
+ breakpoint();
+ #endif
+
+ /* invoke board-specific irq setup */
+ irq_setup();
+ }
+
|
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/dec
In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/dec
Modified Files:
time.c
Log Message:
Sync to 2.4.7
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/dec/time.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** time.c 2001/07/10 16:28:42 1.2
--- time.c 2001/08/25 02:19:27 1.3
***************
*** 32,35 ****
--- 32,37 ----
#include <asm/div64.h>
+ extern void (*board_time_init)(struct irqaction *irq);
+
extern volatile unsigned long wall_jiffies;
extern rwlock_t xtime_lock;
***************
*** 427,432 ****
"timer", NULL, NULL};
- void (*board_time_init) (struct irqaction * irq);
-
void __init time_init(void)
{
--- 429,432 ----
***************
*** 486,488 ****
board_time_init(&irq0);
}
-
--- 486,487 ----
|
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000
In directory usw-pr-cvs1:/tmp/cvs-serv13548/arch/mips/au1000/pb1000
Modified Files:
setup.c
Log Message:
Sync to 2.4.7
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** setup.c 2001/08/23 17:20:04 1.4
--- setup.c 2001/08/25 02:19:27 1.5
***************
*** 63,69 ****
extern void au1000_halt(void);
extern void au1000_power_off(void);
- extern struct resource ioport_resource;
- extern struct resource iomem_resource;
void au1000_wbflush(void)
--- 63,84 ----
extern void au1000_halt(void);
extern void au1000_power_off(void);
+ struct {
+ struct resource ram;
+ struct resource io;
+ struct resource sram;
+ struct resource flash;
+ struct resource boot;
+ struct resource pcmcia;
+ struct resource lcd;
+ } au1000_resources = {
+ { "RAM", 0, 0x3FFFFFF, IORESOURCE_MEM },
+ { "I/O", 0x10000000, 0x119FFFFF },
+ { "SRAM", 0x1e000000, 0x1E03FFFF },
+ { "System Flash", 0x1F800000, 0x1FBFFFFF },
+ { "Boot ROM", 0x1FC00000, 0x1FFFFFFF },
+ { "PCMCIA", 0x20000000, 0x27FFFFFF },
+ { "LCD", 0x60000000, 0x603FFFFF },
+ };
void au1000_wbflush(void)
***************
*** 80,84 ****
#ifdef CONFIG_AU1000_SERIAL_CONSOLE
! if ((argptr = strstr(argptr, "console=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
--- 95,99 ----
#ifdef CONFIG_AU1000_SERIAL_CONSOLE
! if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200");
***************
*** 95,103 ****
* IO/MEM resources.
*/
! mips_io_port_base = 0;
! ioport_resource.start = 0;
! ioport_resource.end = 0xffffffff;
! iomem_resource.start = 0;
! ioport_resource.end = 0xffffffff;
#ifdef CONFIG_BLK_DEV_INITRD
--- 110,116 ----
* IO/MEM resources.
*/
! mips_io_port_base = KSEG1;
! ioport_resource.start = au1000_resources.io.start;
! ioport_resource.end = au1000_resources.lcd.end;
#ifdef CONFIG_BLK_DEV_INITRD
|
|
From: Paul M. <le...@us...> - 2001-08-25 02:19:30
|
Update of /cvsroot/linux-mips/linux In directory usw-pr-cvs1:/tmp/cvs-serv13548 Modified Files: Makefile Log Message: Sync to 2.4.7 Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/Makefile,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** Makefile 2001/08/23 03:17:33 1.2 --- Makefile 2001/08/25 02:19:27 1.3 *************** *** 1,5 **** VERSION = 2 PATCHLEVEL = 4 ! SUBLEVEL = 6 EXTRAVERSION = -mips --- 1,5 ---- VERSION = 2 PATCHLEVEL = 4 ! SUBLEVEL = 7 EXTRAVERSION = -mips *************** *** 89,93 **** CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \ ! -fomit-frame-pointer -fno-strict-aliasing AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) --- 89,93 ---- CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \ ! -fomit-frame-pointer -fno-strict-aliasing -fno-common AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) *************** *** 148,151 **** --- 148,152 ---- DRIVERS-$(CONFIG_IDE) += drivers/ide/idedriver.o DRIVERS-$(CONFIG_SCSI) += drivers/scsi/scsidrv.o + DRIVERS-$(CONFIG_FUSION_BOOT) += drivers/message/fusion/fusion.o DRIVERS-$(CONFIG_IEEE1394) += drivers/ieee1394/ieee1394drv.o *************** *** 334,338 **** etags `find include/asm-$(ARCH) -name '*.h'` find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print | xargs etags -a ! find $(SUBDIRS) init -name '*.c' | xargs etags -a # Exuberant ctags works better with -I --- 335,339 ---- etags `find include/asm-$(ARCH) -name '*.h'` find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print | xargs etags -a ! find $(SUBDIRS) init -name '*.[ch]' | xargs etags -a # Exuberant ctags works better with -I *************** *** 341,345 **** ctags $$CTAGSF `find include/asm-$(ARCH) -name '*.h'` && \ find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print | xargs ctags $$CTAGSF -a && \ ! find $(SUBDIRS) init -name '*.c' | xargs ctags $$CTAGSF -a ifdef CONFIG_MODULES --- 342,346 ---- ctags $$CTAGSF `find include/asm-$(ARCH) -name '*.h'` && \ find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print | xargs ctags $$CTAGSF -a && \ ! find $(SUBDIRS) init -name '*.[ch]' | xargs ctags $$CTAGSF -a ifdef CONFIG_MODULES *************** *** 418,424 **** distclean: mrproper ! rm -f core `find . \( -name '*.orig' -o -name '*.rej' -o -name '*~' \ ! -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \ ! -o -name '.*.rej' -o -name '.SUMS' -o -size 0 \) -type f -print` TAGS tags backup: mrproper --- 419,426 ---- distclean: mrproper ! find . -type f \( -name core -o -name '*.orig' -o -name '*.rej' \ ! -o -name '*~' -o -name '*.bak' -o -name '#*#' \ ! -o -name '.*.orig' -o -name '.*.rej' -o -name '.SUMS' \ ! -o -size 0 -o -name TAGS -o -name tags \) -print | env -i xargs rm -f backup: mrproper *************** *** 442,450 **** sums: ! find . -type f -print | sort | xargs sum > .SUMS dep-files: scripts/mkdep archdep include/linux/version.h scripts/mkdep -- init/*.c > .depend ! scripts/mkdep -- `find $(FINDHPATH) -name SCCS -prune -o -follow -name \*.h ! -name modversions.h -print` > .hdepend $(MAKE) $(patsubst %,_sfdep_%,$(SUBDIRS)) _FASTDEP_ALL_SUB_DIRS="$(SUBDIRS)" ifdef CONFIG_MODVERSIONS --- 444,452 ---- sums: ! find . -type f -print | sort | env -i xargs sum > .SUMS dep-files: scripts/mkdep archdep include/linux/version.h scripts/mkdep -- init/*.c > .depend ! find $(FINDHPATH) -name SCCS -prune -o -follow -name \*.h ! -name modversions.h -print | env -i PATH="$(PATH)" HPATH="$(HPATH)" xargs scripts/mkdep -- > .hdepend $(MAKE) $(patsubst %,_sfdep_%,$(SUBDIRS)) _FASTDEP_ALL_SUB_DIRS="$(SUBDIRS)" ifdef CONFIG_MODVERSIONS |
|
From: James S. <jsi...@us...> - 2001-08-24 19:01:29
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32
In directory usw-pr-cvs1:/tmp/cvs-serv19814
Added Files:
Makefile crime.c ip32-berr.c ip32-irq-glue.S ip32-irq.c
ip32-pci-dma.c ip32-pci.c ip32-rtc.c ip32-setup.c ip32-timer.c
Log Message:
Added sgi ip32 platform.
--- NEW FILE: Makefile ---
#
# Makefile for the SGI specific kernel interface routines
# under Linux.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
# Note 2! The CFLAGS definitions are now in the main makefile...
.S.s:
$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
O_TARGET := ip32-kern.a
all: ip32-kern.a ip32-irq-glue.o
obj-y += ip32-irq.o ip32-rtc.o ip32-setup.o ip32-irq-glue.o \
ip32-berr.o ip32-timer.o crime.o
ifdef CONFIG_PCI
obj-y += ip32-pci.o ip32-pci-dma.o
endif
include $(TOPDIR)/Rules.make
--- NEW FILE: crime.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/ip32/crime.h>
#include <asm/ptrace.h>
#include <asm/promlib.h>
void __init crime_init (void)
{
u64 id = crime_read_64 (CRIME_ID);
u64 rev = id & CRIME_ID_REV;
id = (id & CRIME_ID_IDBITS) >> 4;
printk ("CRIME id %1lx rev %ld detected at %016lx\n", id, rev,
(unsigned long) CRIME_BASE);
}
/* XXX Like on Sun, these give us various useful information to printk. */
void crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
{
u64 memerr = crime_read_64 (CRIME_MEM_ERROR_STAT);
u64 addr = crime_read_64 (CRIME_MEM_ERROR_ADDR);
memerr &= CRIME_MEM_ERROR_STAT_MASK;
printk ("CRIME memory error at physaddr 0x%08lx status %08lx\n",
addr << 2, memerr);
crime_write_64 (CRIME_MEM_ERROR_STAT, 0);
}
void crime_cpuerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
{
u64 cpuerr = crime_read_64 (CRIME_CPU_ERROR_STAT);
u64 addr = crime_read_64 (CRIME_CPU_ERROR_ADDR);
cpuerr &= CRIME_CPU_ERROR_MASK;
addr <<= 2UL;
printk ("CRIME CPU interface error detected at %09lx status %08lx\n",
addr, cpuerr);
crime_write_64 (CRIME_CPU_ERROR_STAT, 0);
}
--- NEW FILE: ip32-berr.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 by Silicon Graphics
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/uaccess.h>
#include <asm/paccess.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
/* XXX I have no idea what this does --kmw */
extern asmlinkage void handle_ibe(void);
extern asmlinkage void handle_dbe(void);
extern const struct exception_table_entry __start___dbe_table[];
extern const struct exception_table_entry __stop___dbe_table[];
static inline unsigned long
search_one_table(const struct exception_table_entry *first,
const struct exception_table_entry *last,
unsigned long value)
{
while (first <= last) {
const struct exception_table_entry *mid;
long diff;
mid = (last - first) / 2 + first;
diff = mid->insn - value;
if (diff == 0)
return mid->nextinsn;
else if (diff < 0)
first = mid+1;
else
last = mid-1;
}
return 0;
}
static inline unsigned long
search_dbe_table(unsigned long addr)
{
unsigned long ret;
/* There is only the kernel to search. */
ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr);
if (ret) return ret;
return 0;
}
void do_ibe(struct pt_regs *regs)
{
printk("Got ibe at 0x%lx\n", regs->cp0_epc);
show_regs(regs);
dump_tlb_addr(regs->cp0_epc);
force_sig(SIGBUS, current);
while(1);
}
void do_dbe(struct pt_regs *regs)
{
unsigned long fixup;
fixup = search_dbe_table(regs->cp0_epc);
if (fixup) {
long new_epc;
new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
regs->cp0_epc = new_epc;
return;
}
printk("Got dbe at 0x%lx\n", regs->cp0_epc);
show_regs(regs);
dump_tlb_all();
while(1);
force_sig(SIGBUS, current);
}
void __init
bus_error_init(void)
{
int dummy;
set_except_vector(6, handle_ibe);
set_except_vector(7, handle_dbe);
/* At this time nothing uses the DBE protection mechanism on the
O2, so this here is needed to make the kernel link. */
get_dbe(dummy, (int *)KSEG0);
}
--- NEW FILE: ip32-irq-glue.S ---
/*
* Low level interrupt handler for the SGI O2 aka IP32 aka Moosehead
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/addrspace.h>
#include <asm/ip32/ip32_ints.h>
.text
.set noreorder
.set noat
.align 5
NESTED(ip32_handle_int, PT_SIZE, ra)
.set noat
SAVE_ALL
CLI # TEST: interrupts should be off
.set at
.set noreorder
mfc0 s0,CP0_CAUSE
andi t1, s0, IE_IRQ0
bnez t1, handle_irq0
andi t1, s0, IE_IRQ1
bnez t1, handle_irq1
andi t1, s0, IE_IRQ2
bnez t1, handle_irq2
andi t1, s0, IE_IRQ3
bnez t1, handle_irq3
andi t1, s0, IE_IRQ4
bnez t1, handle_irq4
andi t1, s0, IE_IRQ5
bnez t1, handle_irq5
nop
/* Either someone has triggered the "software interrupts"
* or we lost an interrupt somehow. Ignore it.
*/
j ret_from_irq
nop
handle_irq0:
jal ip32_irq0
move a0, sp
j ret_from_irq
nop
handle_irq1:
jal ip32_irq1
move a0, sp
j ret_from_irq
nop
handle_irq2:
jal ip32_irq2
move a0, sp
j ret_from_irq
nop
handle_irq3:
jal ip32_irq3
move a0, sp
j ret_from_irq
nop
handle_irq4:
jal ip32_irq4
move a0, sp
j ret_from_irq
nop
handle_irq5:
jal ip32_irq5
move a0, sp
j ret_from_irq
nop
END(ip32_handle_int)
--- NEW FILE: ip32-irq.c ---
/*
* Code to handle IP32 IRQs
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <asm/bitops.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/ip32/ip32_ints.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/signal.h>
#undef DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
/* O2 irq map
*
* IP0 -> software (ignored)
* IP1 -> software (ignored)
* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
* IP3 -> (irq1) X unknown
* IP4 -> (irq2) X unknown
* IP5 -> (irq3) X unknown
* IP6 -> (irq4) X unknown
* IP7 -> (irq5) 0 CPU count/compare timer (system timer)
*
* crime: (C)
*
* CRIME_INT_STAT 31:0:
*
* 0 -> 1 Video in 1
* 1 -> 2 Video in 2
* 2 -> 3 Video out
* 3 -> 4 Mace ethernet
* 4 -> S SuperIO sub-interrupt
* 5 -> M Miscellaneous sub-interrupt
* 6 -> A Audio sub-interrupt
* 7 -> 8 PCI bridge errors
* 8 -> 9 PCI SCSI aic7xxx 0
* 9 -> 10 PCI SCSI aic7xxx 1
* 10 -> 11 PCI slot 0
* 11 -> 12 unused (PCI slot 1)
* 12 -> 13 unused (PCI slot 2)
* 13 -> 14 unused (PCI shared 0)
* 14 -> 15 unused (PCI shared 1)
* 15 -> 16 unused (PCI shared 2)
* 16 -> 17 GBE0 (E)
* 17 -> 18 GBE1 (E)
* 18 -> 19 GBE2 (E)
* 19 -> 20 GBE3 (E)
* 20 -> 21 CPU errors
* 21 -> 22 Memory errors
* 22 -> 23 RE empty edge (E)
* 23 -> 24 RE full edge (E)
* 24 -> 25 RE idle edge (E)
* 25 -> 26 RE empty level
* 26 -> 27 RE full level
* 27 -> 28 RE idle level
* 28 -> 29 unused (software 0) (E)
* 29 -> 30 unused (software 1) (E)
* 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
* 31 -> 32 VICE
*
* S, M, A: Use the MACE ISA interrupt register
* MACE_ISA_INT_STAT 31:0
*
* 0-7 -> 33-40 Audio
* 8 -> 41 RTC
* 9 -> 42 Keyboard
* 10 -> X Keyboard polled
* 11 -> 44 Mouse
* 12 -> X Mouse polled
* 13-15 -> 46-48 Count/compare timers
* 16-19 -> 49-52 Parallel (16 E)
* 20-25 -> 53-58 Serial 1 (22 E)
* 26-31 -> 59-64 Serial 2 (28 E)
*
* Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
* different IRQ map than IRIX uses, but that's OK as Linux irq handling
* is quite different anyway.
*/
/* Some initial interrupts to set up */
extern void crime_memerr_intr (unsigned int irq, void *dev_id,
struct pt_regs *regs);
extern void crime_cpuerr_intr (unsigned int irq, void *dev_id,
struct pt_regs *regs);
struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT,
0, "CRIME memory error", NULL,
NULL };
struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT,
0, "CRIME CPU error", NULL,
NULL };
unsigned long spurious_count = 0;
extern void ip32_handle_int (void);
extern void do_IRQ (unsigned int irq, struct pt_regs *regs);
/* For interrupts wired from a single device to the CPU. Only the clock
* uses this it seems, which is IRQ 0 and IP7.
*/
static void enable_cpu_irq (unsigned int irq)
{
set_cp0_status (STATUSF_IP7);
}
static unsigned int startup_cpu_irq (unsigned int irq) {
enable_cpu_irq (irq);
return 0;
}
static void disable_cpu_irq (unsigned int irq)
{
clear_cp0_status (STATUSF_IP7);
}
static void end_cpu_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_cpu_irq (irq);
}
#define shutdown_cpu_irq disable_cpu_irq
#define mask_and_ack_cpu_irq disable_cpu_irq
static struct hw_interrupt_type ip32_cpu_interrupt = {
"IP32 CPU",
startup_cpu_irq,
shutdown_cpu_irq,
enable_cpu_irq,
disable_cpu_irq,
mask_and_ack_cpu_irq,
end_cpu_irq,
NULL
};
/*
* This is for pure CRIME interrupts - ie not MACE. The advantage?
* We get to split the register in half and do faster lookups.
*/
static void enable_crime_irq (unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
save_and_cli (flags);
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask |= 1 << (irq - 1);
crime_write_64 (CRIME_INT_MASK, crime_mask);
restore_flags (flags);
}
static unsigned int startup_crime_irq (unsigned int irq)
{
enable_crime_irq (irq);
return 0; /* This is probably not right; we could have pending irqs */
}
static void disable_crime_irq (unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
save_and_cli (flags);
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask &= ~(1 << (irq - 1));
crime_write_64 (CRIME_INT_MASK, crime_mask);
restore_flags (flags);
}
static void mask_and_ack_crime_irq (unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
/* Edge triggered interrupts must be cleared. */
if ((irq <= CRIME_GBE0_IRQ && irq >= CRIME_GBE3_IRQ)
|| (irq <= CRIME_RE_EMPTY_E_IRQ && irq >= CRIME_RE_IDLE_E_IRQ)
|| (irq <= CRIME_SOFT0_IRQ && irq >= CRIME_SOFT2_IRQ)) {
save_and_cli (flags);
crime_mask = crime_read_64 (CRIME_HARD_INT);
crime_mask &= ~(1 << (irq - 1));
crime_write_64 (CRIME_HARD_INT, crime_mask);
restore_flags (flags);
}
disable_crime_irq (irq);
}
static void end_crime_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_crime_irq (irq);
}
#define shutdown_crime_irq disable_crime_irq
static struct hw_interrupt_type ip32_crime_interrupt = {
"IP32 CRIME",
startup_crime_irq,
shutdown_crime_irq,
enable_crime_irq,
disable_crime_irq,
mask_and_ack_crime_irq,
end_crime_irq,
NULL
};
/* This is for MACE PCI interrupts. We can decrease bus traffic by masking
* as close to the source as possible. This also means we can take the
* next chunk of the CRIME register in one piece.
*/
static void enable_macepci_irq (unsigned int irq)
{
u32 mace_mask;
u64 crime_mask;
unsigned long flags;
save_and_cli (flags);
mace_mask = mace_read_32 (MACEPCI_CONTROL);
mace_mask |= MACEPCI_CONTROL_INT (irq - 9);
mace_write_32 (MACEPCI_CONTROL, mace_mask);
/* In case the CRIME interrupt isn't enabled, we must enable it;
* however, we never disable interrupts at that level.
*/
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask |= 1 << (irq - 1);
crime_write_64 (CRIME_INT_MASK, crime_mask);
restore_flags (flags);
}
static unsigned int startup_macepci_irq (unsigned int irq) {
enable_macepci_irq (irq);
return 0; /* XXX */
}
static void disable_macepci_irq (unsigned int irq)
{
u32 mace_mask;
unsigned long flags;
save_and_cli (flags);
mace_mask = mace_read_32 (MACEPCI_CONTROL);
mace_mask &= ~MACEPCI_CONTROL_INT (irq - 9);
mace_write_32 (MACEPCI_CONTROL, mace_mask);
restore_flags (flags);
}
static void end_macepci_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_macepci_irq (irq);
}
#define shutdown_macepci_irq disable_macepci_irq
#define mask_and_ack_macepci_irq disable_macepci_irq
static struct hw_interrupt_type ip32_macepci_interrupt = {
"IP32 MACE PCI",
startup_macepci_irq,
shutdown_macepci_irq,
enable_macepci_irq,
disable_macepci_irq,
mask_and_ack_macepci_irq,
end_macepci_irq,
NULL
};
/* This is used for MACE ISA interrupts. That means bits 4-6 in the
* CRIME register.
*/
static void enable_maceisa_irq (unsigned int irq)
{
u64 crime_mask;
u32 mace_mask;
unsigned int crime_int = 0;
unsigned long flags;
DBG ("maceisa enable: %u\n", irq);
switch (irq) {
case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
crime_int = MACE_AUDIO_INT;
break;
case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
crime_int = MACE_MISC_INT;
break;
case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
crime_int = MACE_SUPERIO_INT;
break;
}
DBG ("crime_int %016lx enabled\n", crime_int);
save_and_cli (flags);
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask |= crime_int;
crime_write_64 (CRIME_INT_MASK, crime_mask);
mace_mask = mace_read_32 (MACEISA_INT_MASK);
mace_mask |= 1 << (irq - 33);
mace_write_32 (MACEISA_INT_MASK, mace_mask);
restore_flags (flags);
}
static unsigned int startup_maceisa_irq (unsigned int irq) {
enable_maceisa_irq (irq);
return 0;
}
static void disable_maceisa_irq (unsigned int irq)
{
u32 mace_mask;
unsigned long flags;
save_and_cli (flags);
mace_mask = mace_read_32 (MACEISA_INT_MASK);
mace_mask &= ~(1 << (irq - 33));
mace_write_32 (MACEISA_INT_MASK, mace_mask);
restore_flags (flags);
}
static void mask_and_ack_maceisa_irq (unsigned int irq)
{
u32 mace_mask;
unsigned long flags;
switch (irq) {
case MACEISA_PARALLEL_IRQ:
case MACEISA_SERIAL1_TDMAPR_IRQ:
case MACEISA_SERIAL2_TDMAPR_IRQ:
save_and_cli (flags);
mace_mask = mace_read_32 (MACEISA_INT_STAT);
mace_mask &= ~(1 << (irq - 33));
mace_write_32 (MACEISA_INT_STAT, mace_mask);
restore_flags (flags);
break;
}
disable_maceisa_irq (irq);
}
static void end_maceisa_irq (unsigned irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_maceisa_irq (irq);
}
#define shutdown_maceisa_irq disable_maceisa_irq
static struct hw_interrupt_type ip32_maceisa_interrupt = {
"IP32 MACE ISA",
startup_maceisa_irq,
shutdown_maceisa_irq,
enable_maceisa_irq,
disable_maceisa_irq,
mask_and_ack_maceisa_irq,
end_maceisa_irq,
NULL
};
/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
* bits 0-3 and 7 in the CRIME register.
*/
static void enable_mace_irq (unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
save_and_cli (flags);
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask |= 1 << (irq - 1);
crime_write_64 (CRIME_INT_MASK, crime_mask);
restore_flags (flags);
}
static unsigned int startup_mace_irq (unsigned int irq)
{
enable_mace_irq (irq);
return 0;
}
static void disable_mace_irq (unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
save_and_cli (flags);
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask &= ~(1 << (irq - 1));
crime_write_64 (CRIME_INT_MASK, crime_mask);
restore_flags (flags);
}
static void end_mace_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_mace_irq (irq);
}
#define shutdown_mace_irq disable_mace_irq
#define mask_and_ack_mace_irq disable_mace_irq
static struct hw_interrupt_type ip32_mace_interrupt = {
"IP32 MACE",
startup_mace_irq,
shutdown_mace_irq,
enable_mace_irq,
disable_mace_irq,
mask_and_ack_mace_irq,
end_mace_irq,
NULL
};
static void ip32_unknown_interrupt (struct pt_regs *regs)
{
u64 crime;
u32 mace;
printk ("Unknown interrupt occurred!\n");
printk ("cp0_status: %08x\tcp0_cause: %08x\n",
read_32bit_cp0_register (CP0_STATUS),
read_32bit_cp0_register (CP0_CAUSE));
crime = crime_read_64 (CRIME_INT_MASK);
printk ("CRIME interrupt mask: %016lx\n", crime);
crime = crime_read_64 (CRIME_INT_STAT);
printk ("CRIME interrupt status: %016lx\n", crime);
crime = crime_read_64 (CRIME_HARD_INT);
printk ("CRIME hardware interrupt register: %016lx\n", crime);
mace = mace_read_32 (MACEISA_INT_MASK);
printk ("MACE ISA interrupt mask: %08x\n", mace);
mace = mace_read_32 (MACEISA_INT_STAT);
printk ("MACE ISA interrupt status: %08x\n", mace);
mace = mace_read_32 (MACEPCI_CONTROL);
printk ("MACE PCI control register: %08x\n", mace);
printk ("Register dump:\n");
show_regs (regs);
printk ("Please mail this report to lin...@os...\n");
printk ("Spinning...");
while (1) ;
}
void __init ip32_irq_init(void)
{
unsigned int irq;
extern void init_generic_irq (void);
/* Install our interrupt handler, then clear and disable all
* CRIME and MACE interrupts.
*/
crime_write_64 (CRIME_INT_MASK, 0);
crime_write_64 (CRIME_HARD_INT, 0);
crime_write_64 (CRIME_SOFT_INT, 0);
mace_write_32 (MACEISA_INT_STAT, 0);
mace_write_32 (MACEISA_INT_MASK, 0);
set_except_vector(0, ip32_handle_int);
init_generic_irq ();
for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
hw_irq_controller *controller;
if (irq == CLOCK_IRQ)
controller = &ip32_cpu_interrupt;
else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
controller = &ip32_mace_interrupt;
else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
controller = &ip32_macepci_interrupt;
else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
controller = &ip32_crime_interrupt;
else
controller = &ip32_maceisa_interrupt;
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 0;
irq_desc[irq].handler = controller;
}
setup_irq (CRIME_MEMERR_IRQ, &memerr_irq);
setup_irq (CRIME_CPUERR_IRQ, &cpuerr_irq);
}
/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
void ip32_irq0 (struct pt_regs *regs)
{
u64 crime_int = crime_read_64 (CRIME_INT_STAT);
int irq = 0;
if (crime_int & CRIME_MACE_INT_MASK) {
crime_int &= CRIME_MACE_INT_MASK;
irq = ffs (crime_int);
} else if (crime_int & CRIME_MACEISA_INT_MASK) {
u32 mace_int;
mace_int = mace_read_32 (MACEISA_INT_STAT);
if (mace_int == 0)
irq = 0;
else
irq = ffs (mace_int) + 32;
} else if (crime_int & CRIME_MACEPCI_INT_MASK) {
crime_int &= CRIME_MACEPCI_INT_MASK;
crime_int >>= 8;
irq = ffs (crime_int) + 8;
} else if (crime_int & 0xffff0000) {
crime_int >>= 16;
irq = ffs (crime_int) + 16;
}
if (irq == 0)
ip32_unknown_interrupt (regs);
DBG ("*irq %u*\n", irq);
do_IRQ (irq, regs);
}
void ip32_irq1 (struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
void ip32_irq2 (struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
void ip32_irq3 (struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
void ip32_irq4 (struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
void ip32_irq5 (struct pt_regs *regs)
{
do_IRQ (CLOCK_IRQ, regs);
}
--- NEW FILE: ip32-pci-dma.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Ani Joshi <aj...@un...>
* Copyright (C) 2000 Ralf Baechle <ra...@gn...>
* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
*/
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/ip32/mace.h>
unsigned long bus_to_baddr[256] = { MACEPCI_SWAPPED_VIEW, 0, };
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
gfp |= GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
dma_cache_wback_inv((unsigned long) ret, size);
*dma_handle = (bus_to_baddr[0] | __pa (ret));
}
return ret;
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long) vaddr, get_order(size));
}
--- NEW FILE: ip32-pci.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000, 2001 Keith M Wesolowski
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <asm/pci.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/ip32_ints.h>
#include <linux/delay.h>
#undef DEBUG_MACE_PCI
/*
* O2 has up to 5 PCI devices connected into the MACE bridge. The device
* map looks like this:
*
* 0 aic7xxx 0
* 1 aic7xxx 1
* 2 expansion slot
* 3 N/C
* 4 N/C
*/
#define chkslot(dev) \
do { \
if ((dev)->bus->number > 0 || PCI_SLOT ((dev)->devfn) < 1 \
|| PCI_SLOT ((dev)->devfn) > 3) \
return PCIBIOS_DEVICE_NOT_FOUND; \
} while (0)
#define mkaddr(dev, where) \
((((dev)->devfn & 0xffUL) << 8) | ((where) & 0xfcUL))
void macepci_error (int irq, void *dev, struct pt_regs *regs);
static int macepci_read_config_byte (struct pci_dev *dev, int where,
u8 *val)
{
*val = 0xff;
chkslot (dev);
mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where));
*val = mace_read_8 (MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL));
return PCIBIOS_SUCCESSFUL;
}
static int macepci_read_config_word (struct pci_dev *dev, int where,
u16 *val)
{
*val = 0xffff;
chkslot (dev);
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where));
*val = mace_read_16 (MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL));
return PCIBIOS_SUCCESSFUL;
}
static int macepci_read_config_dword (struct pci_dev *dev, int where,
u32 *val)
{
*val = 0xffffffff;
chkslot (dev);
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where));
*val = mace_read_32 (MACEPCI_CONFIG_DATA);
return PCIBIOS_SUCCESSFUL;
}
static int macepci_write_config_byte (struct pci_dev *dev, int where,
u8 val)
{
chkslot (dev);
mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where));
mace_write_8 (MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL), val);
return PCIBIOS_SUCCESSFUL;
}
static int macepci_write_config_word (struct pci_dev *dev, int where,
u16 val)
{
chkslot (dev);
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where));
mace_write_16 (MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL), val);
return PCIBIOS_SUCCESSFUL;
}
static int macepci_write_config_dword (struct pci_dev *dev, int where,
u32 val)
{
chkslot (dev);
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where));
mace_write_32 (MACEPCI_CONFIG_DATA, val);
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops macepci_ops = {
macepci_read_config_byte,
macepci_read_config_word,
macepci_read_config_dword,
macepci_write_config_byte,
macepci_write_config_word,
macepci_write_config_dword
};
struct pci_fixup pcibios_fixups[] = { { 0 } };
void __init pcibios_init (void)
{
struct pci_dev *dev;
u32 start, size;
u16 cmd;
u32 base_io = 0x3000; /* The first i/o address to assign after SCSI */
u32 base_mem = 0x80100000; /* Likewise */
u32 rev = mace_read_32 (MACEPCI_REV);
int i;
printk ("MACE: PCI rev %d detected at %016lx\n", rev,
(u64) MACE_BASE + MACE_PCI);
/* These are *bus* addresses */
ioport_resource.start = 0;
ioport_resource.end = 0xffffffffUL;
iomem_resource.start = 0x80000000UL;
iomem_resource.end = 0xffffffffUL;
/* Clear any outstanding errors and enable interrupts */
mace_write_32 (MACEPCI_ERROR_ADDR, 0);
mace_write_32 (MACEPCI_ERROR_FLAGS, 0);
mace_write_32 (MACEPCI_CONTROL, 0xff008500);
crime_write_64 (CRIME_HARD_INT, 0UL);
crime_write_64 (CRIME_SOFT_INT, 0UL);
crime_write_64 (CRIME_INT_STAT, 0x000000000000ff00UL);
if (request_irq (MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
"MACE PCI error", NULL))
panic ("PCI bridge can't get interrupt; can't happen.\n");
pci_scan_bus (0, &macepci_ops, NULL);
#ifdef DEBUG_MACE_PCI
pci_for_each_dev (dev) {
printk ("Device: %d/%d/%d ARCS-assigned bus resource map\n",
dev->bus->number, PCI_SLOT (dev->devfn),
PCI_FUNC (dev->devfn));
for (i=0; i < DEVICE_COUNT_RESOURCE; i++) {
if (dev->resource[i].start == 0)
continue;
printk ("%d: %016lx - %016lx (flags %04lx)\n",
i, dev->resource[i].start,
dev->resource[i].end, dev->resource[i].flags);
}
}
#endif
/*
* Assign sane resources to and enable all devices. The requirement
* for the SCSI controllers is well-known: a 256-byte I/O region
* which we must assign, and a 1-page memory region which is
* assigned by the system firmware.
*/
pci_for_each_dev (dev) {
switch (PCI_SLOT (dev->devfn)) {
case 1: /* SCSI bus 0 */
dev->resource[0].start = 0x1000UL;
dev->resource[0].end = 0x10ffUL;
break;
case 2: /* SCSI bus 1 */
dev->resource[0].start = 0x2000UL;
dev->resource[0].end = 0x20ffUL;
break;
default: /* Slots - I guess we have only 1 */
for (i=0; i < 6; i++) {
size = dev->resource[i].end
- dev->resource[i].start;
if (!size
|| !(dev->resource[i].flags
& (IORESOURCE_IO|IORESOURCE_MEM))) {
dev->resource[i].start
= dev->resource[i].end = 0UL;
continue;
}
if (dev->resource[i].flags & IORESOURCE_IO) {
dev->resource[i].start = base_io;
base_io += PAGE_ALIGN (size);
} else {
dev->resource[i].start = base_mem;
base_mem += 0x100000UL;
}
dev->resource[i].end =
dev->resource[i].start + size;
}
break;
}
for (i=0; i < 6; i++) {
if (dev->resource[i].start == 0)
continue;
start = dev->resource[i].start;
if (dev->resource[i].flags & IORESOURCE_IO)
start |= 1;
pci_write_config_dword (dev,
PCI_BASE_ADDRESS_0 + (i << 2), (u32) start);
}
pci_write_config_byte (dev, PCI_CACHE_LINE_SIZE, 0x20);
pci_write_config_byte (dev, PCI_LATENCY_TIMER, 0x30);
pci_read_config_word (dev, PCI_COMMAND, &cmd);
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY);
pci_write_config_word (dev, PCI_COMMAND, cmd);
pci_set_master (dev);
}
#ifdef DEBUG_MACE_PCI
printk ("Triggering PCI bridge interrupt...\n");
mace_write_32 (MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST);
pci_for_each_dev (dev) {
printk ("Device: %d/%d/%d final bus resource map\n",
dev->bus->number, PCI_SLOT (dev->devfn),
PCI_FUNC (dev->devfn));
for (i=0; i < DEVICE_COUNT_RESOURCE; i++) {
if (dev->resource[i].start == 0)
continue;
printk ("%d: %016lx - %016lx (flags %04lx)\n",
i, dev->resource[i].start,
dev->resource[i].end, dev->resource[i].flags);
}
}
#endif
}
/*
* Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of
* the device (1-4 => A-D), tell what irq to use. Note that we don't
* in theory have slots 4 and 5, and we never normally use the shared
* irqs. I suppose a device without a pin A will thank us for doing it
* right if there exists such a broken piece of crap.
*/
static int __init macepci_map_irq (struct pci_dev *dev, u8 slot, u8 pin)
{
chkslot (dev);
if (pin == 0)
pin = 1;
switch (slot) {
case 1:
return MACEPCI_SCSI0_IRQ;
case 2:
return MACEPCI_SCSI1_IRQ;
case 3:
switch (pin) {
case 2:
return MACEPCI_SHARED0_IRQ;
case 3:
return MACEPCI_SHARED1_IRQ;
case 4:
return MACEPCI_SHARED2_IRQ;
case 1:
default:
return MACEPCI_SLOT0_IRQ;
}
case 4:
switch (pin) {
case 2:
return MACEPCI_SHARED2_IRQ;
case 3:
return MACEPCI_SHARED0_IRQ;
case 4:
return MACEPCI_SHARED1_IRQ;
case 1:
default:
return MACEPCI_SLOT1_IRQ;
}
return MACEPCI_SLOT1_IRQ;
case 5:
switch (pin) {
case 2:
return MACEPCI_SHARED1_IRQ;
case 3:
return MACEPCI_SHARED2_IRQ;
case 4:
return MACEPCI_SHARED0_IRQ;
case 1:
default:
return MACEPCI_SLOT2_IRQ;
}
default:
return 0;
}
}
/*
* It's not entirely clear what this does in a system with no bridges.
* In any case, bridges are not supported by Linux in O2.
*/
static u8 __init macepci_swizzle (struct pci_dev *dev, u8 *pinp)
{
if (PCI_SLOT (dev->devfn) == 2)
*pinp = 2;
else
*pinp = 1;
return PCI_SLOT (dev->devfn);
}
/* All devices are enabled during initialization. */
int pcibios_enable_device (struct pci_dev *dev)
{
return PCIBIOS_SUCCESSFUL;
}
char * __init pcibios_setup (char *str)
{
return str;
}
void __init pcibios_align_resource (void *data, struct resource *res,
unsigned long size)
{
}
void __init pcibios_update_resource (struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
}
void __init pcibios_update_irq (struct pci_dev *dev, int irq)
{
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
}
void __init pcibios_fixup_bus (struct pci_bus *b)
{
pci_fixup_irqs (macepci_swizzle, macepci_map_irq);
}
/* XXX anybody know what this is supposed to do? */
void __init pcibios_fixup_pbus_ranges(struct pci_bus * bus,
struct pbus_set_ranges_data * ranges)
{
ranges->io_start -= bus->resource[0]->start;
ranges->io_end -= bus->resource[0]->start;
ranges->mem_start -= bus->resource[1]->start;
ranges->mem_end -= bus->resource[1]->start;
}
/*
* Handle errors from the bridge. This includes master and target aborts,
* various command and address errors, and the interrupt test. This gets
* registered on the bridge error irq. It's conceivable that some of these
* conditions warrant a panic. Anybody care to say which ones?
*/
void macepci_error (int irq, void *dev, struct pt_regs *regs) {
u32 flags, error_addr;
char space;
flags = mace_read_32 (MACEPCI_ERROR_FLAGS);
error_addr = mace_read_32 (MACEPCI_ERROR_ADDR);
if (flags & MACEPCI_ERROR_MEMORY_ADDR)
space = 'M';
else if (flags & MACEPCI_ERROR_CONFIG_ADDR)
space = 'C';
else space = 'X';
if (flags & MACEPCI_ERROR_MASTER_ABORT) {
printk ("MACEPCI: Master abort at 0x%08x (%c)\n", error_addr,
space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_MASTER_ABORT);
}
if (flags & MACEPCI_ERROR_TARGET_ABORT) {
printk ("MACEPCI: Target abort at 0x%08x (%c)\n", error_addr,
space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_TARGET_ABORT);
}
if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) {
printk ("MACEPCI: Data parity error at 0x%08x (%c)\n",
error_addr, space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_DATA_PARITY_ERR);
}
if (flags & MACEPCI_ERROR_RETRY_ERR) {
printk ("MACEPCI: Retry error at 0x%08x (%c)\n", error_addr,
space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_RETRY_ERR);
}
if (flags & MACEPCI_ERROR_ILLEGAL_CMD) {
printk ("MACEPCI: Illegal command at 0x%08x (%c)\n",
error_addr, space);
mace_write_32 (MACEPCI_ERROR_FLAGS,
flags & ~MACEPCI_ERROR_ILLEGAL_CMD);
}
if (flags & MACEPCI_ERROR_SYSTEM_ERR) {
printk ("MACEPCI: System error at 0x%08x (%c)\n",
error_addr, space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_SYSTEM_ERR);
}
if (flags & MACEPCI_ERROR_PARITY_ERR) {
printk ("MACEPCI: Parity error at 0x%08x (%c)\n", error_addr,
space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_PARITY_ERR);
}
if (flags & MACEPCI_ERROR_OVERRUN) {
printk ("MACEPCI: Overrun error at 0x%08x (%c)\n",
error_addr, space);
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_OVERRUN);
}
if (flags & MACEPCI_ERROR_SIG_TABORT) {
printk ("MACEPCI: Signaled target abort (clearing)\n");
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_SIG_TABORT);
}
if (flags & MACEPCI_ERROR_INTERRUPT_TEST) {
printk ("MACEPCI: Interrupt test triggered (clearing)\n");
mace_write_32 (MACEPCI_ERROR_FLAGS, flags
& ~MACEPCI_ERROR_INTERRUPT_TEST);
}
}
--- NEW FILE: ip32-rtc.c ---
/*
* RTC routines for IP32 style attached Dallas chip.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#include <linux/mc146818rtc.h>
#include <asm/ip32/mace.h>
static unsigned char ip32_rtc_read_data(unsigned long addr)
{
return (unsigned char) mace_read_8 (MACEISA_RTC_BASE + (addr << 8));
}
static void ip32_rtc_write_data(unsigned char data, unsigned long addr)
{
mace_write_8 (MACEISA_RTC_BASE + (addr << 8), data);
}
static int ip32_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops ip32_rtc_ops = {
&ip32_rtc_read_data,
&ip32_rtc_write_data,
&ip32_rtc_bcd_mode
};
--- NEW FILE: ip32-setup.c ---
/*
* IP32 basic setup
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
#include <asm/sgialib.h>
extern struct rtc_ops ip32_rtc_ops;
extern u32 cc_interval;
void __init ip32_init (int argc, char **argv, char **envp) {
arc_meminit ();
}
void __init ip32_setup(void)
{
#ifdef CONFIG_SERIAL_CONSOLE
char *ctype;
#endif
TLBMISS_HANDLER_SETUP ();
#ifdef CONFIG_SERIAL_CONSOLE
ctype = ArcGetEnvironmentVariable("console");
if (*ctype == 'd') {
if (ctype[1] == '2')
console_setup ("ttyS1");
else
console_setup ("ttyS0");
}
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
rtc_ops = &ip32_rtc_ops;
crime_init ();
}
int __init page_is_ram (unsigned long pagenr)
{
/* XXX: to do? */
return 1;
}
--- NEW FILE: ip32-timer.c ---
/*
* IP32 timer calibration
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mipsregs.h>
#include <asm/param.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/ip32_ints.h>
extern u32 cc_interval;
/* An arbitrary time; this can be decreased if reliability looks good */
#define WAIT_MS 10
#define PER_MHZ (1000000 / 2 / HZ)
void __init ip32_timer_setup (struct irqaction *irq) {
u64 crime_time;
u32 cc_tick;
printk("Calibrating system timer... ");
crime_time = crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK;
cc_tick = read_32bit_cp0_register (CP0_COUNT);
while ((crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK) - crime_time
< WAIT_MS * 1000000 / CRIME_NS_PER_TICK)
;
cc_tick = read_32bit_cp0_register (CP0_COUNT) - cc_tick;
cc_interval = cc_tick / HZ * (1000 / WAIT_MS);
/* The round-off seems unnecessary; in testing, the error of the
* above procedure is < 100 ticks, which means it gets filtered
* out by the HZ adjustment.
*/
cc_interval = (cc_interval / PER_MHZ) * PER_MHZ;
printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ));
setup_irq (CLOCK_IRQ, irq);
}
|
|
From: James S. <jsi...@us...> - 2001-08-24 18:59:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64
In directory usw-pr-cvs1:/tmp/cvs-serv19394
Modified Files:
Makefile config.in defconfig defconfig-ip22 defconfig-ip27
Added Files:
defconfig-ip32
Log Message:
Synced to Ralph's tree.
--- NEW FILE: defconfig-ip32 ---
#
# Automatically generated make config: don't edit
#
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# Machine selection
#
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
CONFIG_SGI_IP32=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
CONFIG_BOOT_ELF32=y
CONFIG_ARC32=y
CONFIG_PC_KEYB=y
CONFIG_PCI=y
CONFIG_ARC_MEMORY=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
#
# CPU selection
#
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
#
# General setup
#
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_MIPS_FPU_EMULATOR is not set
CONFIG_NET=y
CONFIG_PCI_NAMES=y
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSCTL=y
# CONFIG_PROM_CONSOLE is not set
CONFIG_BINFMT_ELF=y
CONFIG_MIPS32_COMPAT=y
CONFIG_BINFMT_ELF32=y
CONFIG_BINFMT_MISC=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
CONFIG_PCI_NAMES=y
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
# CONFIG_NETLINK is not set
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
#
#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
CONFIG_CHR_DEV_ST=y
CONFIG_CHR_DEV_OSST=y
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_SR_EXTRA_DEVS=2
CONFIG_CHR_DEV_SG=y
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
CONFIG_SCSI_DEBUG_QUEUES=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
#
# SCSI low-level drivers
#
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
CONFIG_SCSI_AIC7XXX=y
CONFIG_AIC7XXX_CMDS_PER_DEVICE=8
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_NCR53C8XX is not set
# CONFIG_SCSI_SYM53C8XX is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_DEBUG is not set
#
# I2O device support
#
# CONFIG_I2O is not set
# CONFIG_I2O_PCI is not set
# CONFIG_I2O_BLOCK is not set
# CONFIG_I2O_LAN is not set
# CONFIG_I2O_SCSI is not set
# CONFIG_I2O_PROC is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_NET_SB1000 is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_AT1700 is not set
# CONFIG_DEPCA is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_APRICOT is not set
# CONFIG_CS89x0 is not set
CONFIG_TULIP=y
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
# CONFIG_DM9102 is not set
CONFIG_EEPRO100=y
# CONFIG_EEPRO100_PM is not set
# CONFIG_LNE390 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_NE3210 is not set
# CONFIG_ES3210 is not set
# CONFIG_8139TOO is not set
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_LAN_SAA9730 is not set
# CONFIG_NET_POCKET is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
#
# CONFIG_CD_NO_IDESCSI is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
CONFIG_MOUSE=y
CONFIG_PSMOUSE=y
# CONFIG_82C710_MOUSE is not set
# CONFIG_PC110_PAD is not set
#
# Joysticks
#
# CONFIG_JOYSTICK is not set
#
# Input core support is needed for joysticks
#
# CONFIG_QIC02_TAPE is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# File systems
#
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_CRAMFS is not set
CONFIG_TMPFS=y
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_SYSV_FS_WRITE is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
# CONFIG_SMB_FS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
# CONFIG_MSDOS_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
CONFIG_KCORE_ELF=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# Input core support
#
# CONFIG_INPUT is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_REMOTE_DEBUG is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MIPS_UNCACHED=y
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Makefile 2001/06/22 02:29:32 1.1.1.1
--- Makefile 2001/08/24 18:59:54 1.2
***************
*** 85,89 ****
ifdef CONFIG_SGI_IP27
! LIBS += arch/mips64/sgi-ip27/ip27.a arch/mips64/arc/arclib.a
SUBDIRS += arch/mips64/sgi-ip27 arch/mips64/arc
#
--- 85,90 ----
ifdef CONFIG_SGI_IP27
! CORE_FILES += arch/mips64/sgi-ip27/ip27.o
! LIBS += arch/mips64/arc/arclib.a
SUBDIRS += arch/mips64/sgi-ip27 arch/mips64/arc
#
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/config.in,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** config.in 2001/06/22 02:29:32 1.1.1.1
--- config.in 2001/08/24 18:59:54 1.2
***************
*** 271,275 ****
bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ
! if [ "$CONFIG_SMP" != "n" ]; then
bool 'Run uncached' CONFIG_MIPS_UNCACHED
fi
--- 271,275 ----
bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ
! if [ "$CONFIG_SMP" != "y" ]; then
bool 'Run uncached' CONFIG_MIPS_UNCACHED
fi
Index: defconfig
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/defconfig,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** defconfig 2001/08/22 18:18:14 1.2
--- defconfig 2001/08/24 18:59:54 1.3
***************
*** 269,272 ****
--- 269,273 ----
# CONFIG_ACENIC is not set
# CONFIG_ACENIC_OMIT_TIGON_I is not set
+ # CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_HAMACHI is not set
***************
*** 450,453 ****
--- 451,455 ----
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
+ # CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
***************
*** 478,480 ****
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_MAGIC_SYSRQ is not set
- # CONFIG_MIPS_UNCACHED is not set
--- 480,481 ----
Index: defconfig-ip22
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/defconfig-ip22,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** defconfig-ip22 2001/08/22 18:18:14 1.2
--- defconfig-ip22 2001/08/24 18:59:54 1.3
***************
*** 270,273 ****
--- 270,274 ----
# CONFIG_ACENIC is not set
# CONFIG_ACENIC_OMIT_TIGON_I is not set
+ # CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_HAMACHI is not set
***************
*** 360,363 ****
--- 361,365 ----
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
+ # CONFIG_SONYPI is not set
#
***************
*** 453,456 ****
--- 455,459 ----
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
+ # CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
Index: defconfig-ip27
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/defconfig-ip27,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** defconfig-ip27 2001/08/22 18:18:14 1.2
--- defconfig-ip27 2001/08/24 18:59:54 1.3
***************
*** 269,272 ****
--- 269,273 ----
# CONFIG_ACENIC is not set
# CONFIG_ACENIC_OMIT_TIGON_I is not set
+ # CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_HAMACHI is not set
***************
*** 450,453 ****
--- 451,455 ----
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
+ # CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
***************
*** 478,480 ****
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_MAGIC_SYSRQ is not set
- # CONFIG_MIPS_UNCACHED is not set
--- 480,481 ----
|
|
From: James S. <jsi...@us...> - 2001-08-24 18:59:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv19394/kernel
Modified Files:
proc.c ptrace.c unaligned.c
Log Message:
Synced to Ralph's tree.
Index: proc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/proc.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** proc.c 2001/07/09 19:28:47 1.2
--- proc.c 2001/08/24 18:59:54 1.3
***************
*** 4,10 ****
* for more details.
*
! * Copyright (C) 1995, 1996, 1999 Ralf Baechle
! *
! * XXX Rewrite this mess.
*/
#include <linux/delay.h>
--- 4,9 ----
* for more details.
*
! * Copyright (C) 1995, 1996, 1999, 2001 Ralf Baechle
! * Copyright (C) 2001 MIPS Technologies, Inc.
*/
#include <linux/delay.h>
***************
*** 17,21 ****
#include <asm/watch.h>
! unsigned long unaligned_instructions;
unsigned int vced_count, vcei_count;
--- 16,20 ----
#include <asm/watch.h>
! extern unsigned long unaligned_instructions;
unsigned int vced_count, vcei_count;
Index: ptrace.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/ptrace.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** ptrace.c 2001/07/26 16:42:40 1.1
--- ptrace.c 2001/08/24 18:59:54 1.2
***************
*** 63,92 ****
if (request == PTRACE_ATTACH) {
! if (child == current)
! goto out_tsk;
! if ((!child->dumpable ||
! (current->uid != child->euid) ||
! (current->uid != child->suid) ||
! (current->uid != child->uid) ||
! (current->gid != child->egid) ||
! (current->gid != child->sgid) ||
! (!cap_issubset(child->cap_permitted, current->cap_permitted)) ||
! (current->gid != child->gid)) && !capable(CAP_SYS_PTRACE))
! goto out_tsk;
! /* the same process cannot be attached many times */
! if (child->ptrace & PT_PTRACED)
! goto out_tsk;
! child->ptrace |= PT_PTRACED;
!
! write_lock_irq(&tasklist_lock);
! if (child->p_pptr != current) {
! REMOVE_LINKS(child);
! child->p_pptr = current;
! SET_LINKS(child);
! }
! write_unlock_irq(&tasklist_lock);
!
! send_sig(SIGSTOP, child, 1);
! ret = 0;
goto out_tsk;
}
--- 63,67 ----
if (request == PTRACE_ATTACH) {
! ret = ptrace_attach(child);
goto out_tsk;
}
***************
*** 359,388 ****
if (request == PTRACE_ATTACH) {
! if (child == current)
! goto out_tsk;
! if ((!child->dumpable ||
! (current->uid != child->euid) ||
! (current->uid != child->suid) ||
! (current->uid != child->uid) ||
! (current->gid != child->egid) ||
! (current->gid != child->sgid) ||
! (!cap_issubset(child->cap_permitted, current->cap_permitted)) ||
! (current->gid != child->gid)) && !capable(CAP_SYS_PTRACE))
! goto out_tsk;
! /* the same process cannot be attached many times */
! if (child->ptrace & PT_PTRACED)
! goto out_tsk;
! child->ptrace |= PT_PTRACED;
!
! write_lock_irq(&tasklist_lock);
! if (child->p_pptr != current) {
! REMOVE_LINKS(child);
! child->p_pptr = current;
! SET_LINKS(child);
! }
! write_unlock_irq(&tasklist_lock);
!
! send_sig(SIGSTOP, child, 1);
! ret = 0;
goto out_tsk;
}
--- 334,338 ----
if (request == PTRACE_ATTACH) {
! ret = ptrace_attach(child);
goto out_tsk;
}
***************
*** 427,430 ****
--- 377,383 ----
case FPR_BASE ... FPR_BASE + 31:
if (child->used_math) {
+ unsigned long long *fregs
+ = (unsigned long long *)
+ &child->thread.fpu.hard.fp_regs[0];
#ifndef CONFIG_SMP
if (last_task_used_math == child) {
Index: unaligned.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/unaligned.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** unaligned.c 2001/06/22 02:29:32 1.1.1.1
--- unaligned.c 2001/08/24 18:59:54 1.2
***************
*** 73,76 ****
--- 73,77 ----
* Undo the partial store in this case.
*/
+ #include <linux/config.h>
#include <linux/mm.h>
#include <linux/signal.h>
***************
*** 379,383 ****
--- 380,386 ----
}
+ #ifdef CONFIG_PROC_FS
unsigned long unaligned_instructions;
+ #endif
asmlinkage void do_ade(struct pt_regs *regs)
***************
*** 400,404 ****
--- 403,409 ----
emulate_load_store_insn(regs, regs->cp0_badvaddr, pc);
+ #ifdef CONFIG_PROC_FS
unaligned_instructions++;
+ #endif
return;
|
|
From: James S. <jsi...@us...> - 2001-08-24 18:59:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27 In directory usw-pr-cvs1:/tmp/cvs-serv19394/sgi-ip27 Modified Files: ip27-irq.c Log Message: Synced to Ralph's tree. Index: ip27-irq.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-irq.c,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** ip27-irq.c 2001/08/22 18:18:14 1.2 --- ip27-irq.c 2001/08/24 18:59:54 1.3 *************** *** 45,48 **** --- 45,52 ---- #endif + /* These should die */ + unsigned char bus_to_wid[256]; /* widget id for linux pci bus */ + unsigned char bus_to_nid[256]; /* nasid for linux pci bus */ + unsigned char num_bridges; /* number of bridges in the system */ /* |
|
From: James S. <jsi...@us...> - 2001-08-24 17:58:48
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32 In directory usw-pr-cvs1:/tmp/cvs-serv6035/sgi-ip32 Log Message: Directory /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32 added to the repository |
|
From: James S. <jsi...@us...> - 2001-08-23 23:39:54
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv29445
Modified Files:
pci.c
Log Message:
Removed MIPS_ASSERT. It only exist for the ddb5xxx platform.
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** pci.c 2001/07/07 19:37:24 1.1
--- pci.c 2001/08/23 23:39:51 1.2
***************
*** 1,3 ****
! /***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
--- 1,3 ----
! /*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
***************
*** 11,15 ****
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
- ***********************************************************************
*/
--- 11,14 ----
***************
*** 27,31 ****
* later use by Linux.
*
! * . We finally reply on a board supplied function, pcibios_fixup_irq(), to
* to assign the interrupts. We may use setup-irq.c under drivers/pci
* later.
--- 26,30 ----
* later use by Linux.
*
! * . We finally reply on a board supplied function, pcibios_fixup_irq(), to
* to assign the interrupts. We may use setup-irq.c under drivers/pci
* later.
***************
*** 37,43 ****
* Limitations:
*
! * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus
! * into a contiguous range.
! *
* . In the case of Memory space, the rnage is 1:1 mapping with CPU physical
* address space.
--- 36,42 ----
* Limitations:
*
! * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus
! * into a contiguous range.
! *
* . In the case of Memory space, the rnage is 1:1 mapping with CPU physical
* address space.
***************
*** 57,61 ****
* David Mosberger da...@cs...
*/
-
#include <linux/kernel.h>
#include <linux/init.h>
--- 56,59 ----
***************
*** 73,78 ****
};
-
extern int pciauto_assign_resources(int busno, struct pci_channel * hose);
void __init pcibios_init(void)
{
--- 71,76 ----
};
extern int pciauto_assign_resources(int busno, struct pci_channel * hose);
+
void __init pcibios_init(void)
{
***************
*** 108,160 ****
}
! unsigned long __init
! pci_bridge_check_io(struct pci_dev *bridge)
{
! u16 io;
! pci_read_config_word(bridge, PCI_IO_BASE, &io);
! if (!io) {
! pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
! pci_read_config_word(bridge, PCI_IO_BASE, &io);
! pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
! }
! if (io)
! return IORESOURCE_IO;
! printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
! bridge->name);
! return 0;
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
! /* Propogate hose info into the subordinate devices. */
! struct pci_channel *hose = bus->sysdata;
! struct pci_dev *dev = bus->self;
! if (!dev) {
! /* Root bus */
! bus->resource[0] = hose->io_resource;
! bus->resource[1] = hose->mem_resource;
! } else {
! /* This is a bridge. Do not care how it's initialized,
! just link its resources to the bus ones */
! int i;
! for(i=0; i<3; i++) {
! bus->resource[i] =
! &dev->resource[PCI_BRIDGE_RESOURCES+i];
! bus->resource[i]->name = bus->name;
! }
! bus->resource[0]->flags |= pci_bridge_check_io(dev);
! bus->resource[1]->flags |= IORESOURCE_MEM;
! /* For now, propogate hose limits to the bus;
! we'll adjust them later. */
! bus->resource[0]->end = hose->io_resource->end;
! bus->resource[1]->end = hose->mem_resource->end;
! /* Turn off downstream PF memory address range by default */
! bus->resource[2]->start = 1024*1024;
! bus->resource[2]->end = bus->resource[2]->start - 1;
! }
}
--- 106,157 ----
}
! unsigned long __init pci_bridge_check_io(struct pci_dev *bridge)
{
! u16 io;
! pci_read_config_word(bridge, PCI_IO_BASE, &io);
! if (!io) {
! pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
! pci_read_config_word(bridge, PCI_IO_BASE, &io);
! pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
! }
! if (io)
! return IORESOURCE_IO;
! printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
! bridge->name);
! return 0;
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
! /* Propogate hose info into the subordinate devices. */
! struct pci_channel *hose = bus->sysdata;
! struct pci_dev *dev = bus->self;
! if (!dev) {
! /* Root bus */
! bus->resource[0] = hose->io_resource;
! bus->resource[1] = hose->mem_resource;
! } else {
! /* This is a bridge. Do not care how it's initialized,
! just link its resources to the bus ones */
! int i;
! for(i=0; i<3; i++) {
! bus->resource[i] =
! &dev->resource[PCI_BRIDGE_RESOURCES+i];
! bus->resource[i]->name = bus->name;
! }
! bus->resource[0]->flags |= pci_bridge_check_io(dev);
! bus->resource[1]->flags |= IORESOURCE_MEM;
! /* For now, propogate hose limits to the bus;
! we'll adjust them later. */
! bus->resource[0]->end = hose->io_resource->end;
! bus->resource[1]->end = hose->mem_resource->end;
! /* Turn off downstream PF memory address range by default */
! bus->resource[2]->start = 1024*1024;
! bus->resource[2]->end = bus->resource[2]->start - 1;
! }
}
***************
*** 168,179 ****
{
/* this should not be called */
- MIPS_ASSERT(1 == 0);
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
! struct resource *res, int resource)
{
/* this should not be called */
- MIPS_ASSERT(1 == 0);
}
--- 165,174 ----
{
/* this should not be called */
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
! struct resource *res, int resource)
{
/* this should not be called */
}
|
|
From: Jun S. <ju...@us...> - 2001-08-23 23:27:17
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv26871/arch/mips/kernel
Modified Files:
sysmips.c
Log Message:
Dilema between 'R' and 'm'. 'R' is in theory more correct constraint
but does not work in 2.95. 'm' works now. There are other places
which may need the same change, such as xchg_u32() in system.h.
Index: sysmips.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/sysmips.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** sysmips.c 2001/08/23 19:07:28 1.5
--- sysmips.c 2001/08/23 23:27:14 1.6
***************
*** 119,123 ****
".word 2b,4b\n\t"
".previous"
! : "=&r" (ret), "=R" (*ptr), "=r" (err), "=&r" (tmp)
: "r" (val), "1" (*ptr), "2" (0), "i" (-EFAULT));
#else
--- 119,123 ----
".word 2b,4b\n\t"
".previous"
! : "=&r" (ret), "=m" (*ptr), "=r" (err), "=&r" (tmp)
: "r" (val), "1" (*ptr), "2" (0), "i" (-EFAULT));
#else
|
|
From: Jun S. <ju...@us...> - 2001-08-23 19:15:25
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv27933 Added Files: defconfig-korva Log Message: Add defconfig for Korva. We still need to do something with serial setup before we can compile korva out of box. --- NEW FILE: defconfig-korva --- # # Automatically generated by make menuconfig: don't edit # CONFIG_MIPS=y # CONFIG_SMP is not set # # Code maturity level options # CONFIG_EXPERIMENTAL=y # # Machine selection # # CONFIG_ACER_PICA_61 is not set # CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set # CONFIG_NEC_OSPREY is not set # CONFIG_NEC_EAGLE is not set CONFIG_NEC_KORVA=y # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set # CONFIG_SBUS is not set CONFIG_CPU_VR41XX=y CONFIG_SERIAL=y CONFIG_NEW_IRQ=y CONFIG_NEW_TIME_C=y # CONFIG_SCSI is not set # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_PCI is not set # CONFIG_I8259 is not set # # Loadable module support # CONFIG_MODULES=y # CONFIG_MODVERSIONS is not set CONFIG_KMOD=y # # CPU selection # # CONFIG_CPU_R3000 is not set # CONFIG_CPU_R6000 is not set CONFIG_CPU_VR41XX=y # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set # CONFIG_CPU_HAS_LLSC is not set # CONFIG_CPU_HAS_LLDSCD is not set # CONFIG_CPU_HAS_WB is not set # # General setup # CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_KCORE_ELF=y CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set CONFIG_NET=y # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Block devices # # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # CONFIG_BLK_DEV_MD is not set # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID5 is not set # CONFIG_BLK_DEV_LVM is not set # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set # CONFIG_NETLINK is not set # CONFIG_NETFILTER is not set # CONFIG_FILTER is not set CONFIG_UNIX=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set # CONFIG_IPV6 is not set # CONFIG_KHTTPD is not set # CONFIG_ATM is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set # CONFIG_NET_HW_FLOWCONTROL is not set # # QoS and/or fair queueing # # CONFIG_NET_SCHED is not set # # Telephony Support # # CONFIG_PHONE is not set # CONFIG_PHONE_IXJ is not set # # ATA/IDE/MFM/RLL support # # CONFIG_IDE is not set # CONFIG_BLK_DEV_IDE_MODES is not set # CONFIG_BLK_DEV_HD is not set # # SCSI support # # CONFIG_SCSI is not set # # I2O device support # # CONFIG_I2O is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_LAN is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # # Network device support # CONFIG_NETDEVICES=y # # ARCnet devices # # CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y # CONFIG_ARM_AM79C961A is not set # CONFIG_SUNLANCE is not set # CONFIG_SUNBMAC is not set # CONFIG_SUNQE is not set # CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set # CONFIG_NET_POCKET is not set CONFIG_NEC_CANDY=y # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_ACENIC_OMIT_TIGON_I is not set # CONFIG_MYRI_SBUS is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # # Wireless LAN (non-hamradio) # # CONFIG_NET_RADIO is not set # # Token Ring devices # # CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # # Wan interfaces # # CONFIG_WAN is not set # # Amateur Radio support # # CONFIG_HAMRADIO is not set # # IrDA (infrared) support # # CONFIG_IRDA is not set # # ISDN subsystem # # CONFIG_ISDN is not set # # Old CD-ROM drivers (not SCSI, not IDE) # # CONFIG_CD_NO_IDESCSI is not set # # Character devices # # CONFIG_VT is not set CONFIG_SERIAL=y CONFIG_SERIAL_CONSOLE=y CONFIG_SERIAL_NUM_PORTS=1 # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 # # I2C support # # CONFIG_I2C is not set # # Mice # # CONFIG_BUSMOUSE is not set CONFIG_MOUSE=y CONFIG_PSMOUSE=y # CONFIG_82C710_MOUSE is not set # CONFIG_PC110_PAD is not set # # Joysticks # # CONFIG_JOYSTICK is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # File systems # # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set # CONFIG_RAMFS is not set # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set # # Network File Systems # # CONFIG_CODA_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y CONFIG_LOCKD=y # CONFIG_SMB_FS is not set # CONFIG_NCP_FS is not set # CONFIG_NCPFS_PACKET_SIGNING is not set # CONFIG_NCPFS_IOCTL_LOCKING is not set # CONFIG_NCPFS_STRONG is not set # CONFIG_NCPFS_NFS_NS is not set # CONFIG_NCPFS_OS2_NS is not set # CONFIG_NCPFS_SMALLDOS is not set # CONFIG_NCPFS_NLS is not set # CONFIG_NCPFS_EXTRAS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set # # Sound # # CONFIG_SOUND is not set # # USB support # # CONFIG_USB is not set # # Input core support # # CONFIG_INPUT is not set # # Kernel hacking # CONFIG_CROSSCOMPILE=y # CONFIG_REMOTE_DEBUG is not set # CONFIG_GDB_CONSOLE is not set CONFIG_LL_DEBUG=y # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set |
Update of /cvsroot/linux-mips/linux/arch/mips/korva
In directory usw-pr-cvs1:/tmp/cvs-serv27423/arch/mips/korva
Added Files:
Makefile dbg_io.c int_handler.S irq.c irq_cpu.c irq_korva.c
prom.c reset.c setup.c
Log Message:
Support NEC Korva board (vr4120a based).
--- NEW FILE: Makefile ---
#
# Makefile for common code of NEC Korva board
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
.S.s:
$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
$(CC) $(CFLAGS) -c $< -o $*.o
O_TARGET:= korva.a
obj-y := setup.o prom.o reset.o int_handler.o irq.o irq_cpu.o irq_korva.o
obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
include $(TOPDIR)/Rules.make
--- NEW FILE: dbg_io.c ---
#include <linux/config.h>
#if defined(CONFIG_REMOTE_DEBUG)
/* --- CONFIG --- */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the debug board serial port for kdb */
#define BASE 0xb0000080
#define MAX_BAUD 1152000
#define REG_OFFSET 4
static int remoteDebugInitialized = 0;
#define BAUD_DEFAULT UART16550_BAUD_115200
/* === END OF CONFIG === */
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
--- NEW FILE: int_handler.S ---
/*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* First-level&2nd-level interrupt dispatcher for ddb5477
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* The second level IRQ has 5 interrupt sources. So we simply lump
* it together here with the first level.
*
* The IRQ levels are hardcoded. If you change them here, you better
* change the init_IRQ() as well.
*
* CPU IRQs :
* 0 - software intr 0
* 1 - software intr 1
* 2 - ATM Cell Processor
* 3 - USB Controller
* 4 - Ether Controller #1
* 5 - Ether Controller #2
* 6 - cascading to 2nd level (korva) interrupts
* 7 - cpu timer
*
* Korva IRQs :
* 8 - Timer ch0
* 9 - Timer ch1
* 10 - UART
* 11 - External interrupt
* 12 - Wakeup
*/
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/korva.h>
/*
* first level interrupt dispatcher for ocelot board -
* We check for the timer first, then check PCI ints A and D.
* Then check for serial IRQ and fall through.
*/
.align 5
NESTED(korva_handle_irq, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
.set noreorder
mfc0 t0, CP0_CAUSE
mfc0 t2, CP0_STATUS
and t0, t2
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
andi t1, t0, STATUSF_IP2
bnez t1, ll_cpu_ip2
andi t1, t0, STATUSF_IP3
bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP4
bnez t1, ll_cpu_ip4
andi t1, t0, STATUSF_IP5
bnez t1, ll_cpu_ip5
andi t1, t0, STATUSF_IP6
bnez t1, ll_cpu_ip6
andi t1, t0, STATUSF_IP0 /* software int 0 */
bnez t1, ll_cpu_ip0
andi t1, t0, STATUSF_IP1 /* software int 1 */
bnez t1, ll_cpu_ip1
nop
.set reorder
/* wrong alarm or masked ... */
j spurious_interrupt
nop
END(korva_handle_irq)
.align 5
ll_cputimer_irq:
li a0, 7
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip0:
li a0, 0
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip1:
li a0, 1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip2:
li a0, 2
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip3:
li a0, 3
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip4:
li a0, 4
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip5:
li a0, 5
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip6:
/* it is korva 2nd level interrupts */
/* reading ISR will clear it */
la t0, KORVA_BASE_VIRT + KORVA_S_ISR
lw s0, 0(t0)
/* and with the mask - just to be safe */
la t0, KORVA_BASE_VIRT + KORVA_S_IMR
lw t0, 0(t0)
and s0, s0, t0
/* do we need to deliver all the pending ones? */
li a0, 8
li a1, 13
li t0, 1
loop:
and t1, t0, s0
bnez t1, foundone
sll t0, t0, 1
addiu a0, a0, 1
/* check if we reach the end */
beq a0, a1, error
j loop
foundone:
move a1, sp
jal do_IRQ
j ret_from_irq
error:
j spurious_interrupt
--- NEW FILE: irq.c ---
/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* init_IRQ for korva.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/random.h>
#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>
#include <asm/korva.h>
extern asmlinkage void korva_handle_irq(void);
extern void breakpoint(void);
extern void mips_cpu_irq_init(u32 irq_base);
extern void korva_irq_init(u32 irq_base);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL };
void __init init_IRQ(void)
{
set_except_vector(0, korva_handle_irq);
mips_cpu_irq_init(0);
korva_irq_init(8);
/* hack - enable uart */
/* korva_out32(KORVA_S_IMR, 1 << 2); */
/* setup cascade interrupt 6 */
setup_irq(6, &irq2);
#ifdef CONFIG_REMOTE_DEBUG
printk("Setting debug traps - please connect the remote debugger.\n");
set_debug_traps();
// you may move this line to whereever you want
breakpoint();
#endif
}
--- NEW FILE: irq_cpu.c ---
/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* This file define the irq handler for MIPS CPU interrupts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* Almost all MIPS CPUs define 8 interrupt sources. They are typically
* level triggered (i.e., cannot be cleared from CPU; must be cleared from
* device). The first two are software interrupts. The last one is
* usually cpu timer interrupt if coutner register is present.
*
* This file exports one global function:
* mips_cpu_irq_init(u32 irq_base);
*/
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/mipsregs.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
#include <asm/ddb5xxx/debug.h>
static int mips_cpu_irq_base=-1;
static void
mips_cpu_irq_enable(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
static void
mips_cpu_irq_disable(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
static unsigned int mips_cpu_irq_startup(unsigned int irq)
{
mips_cpu_irq_enable(irq);
return 0;
}
#define mips_cpu_irq_shutdown mips_cpu_irq_disable
static void
mips_cpu_irq_ack(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
/* although we attemp to clear the IP bit in cause reigster, I think
* usually it is cleared by device (irq source)
*/
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
/* disable this interrupt - so that we safe proceed to the handler */
mips_cpu_irq_disable(irq);
}
static void
mips_cpu_irq_end(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
mips_cpu_irq_enable(irq);
}
static hw_irq_controller mips_cpu_irq_controller = {
"CPU_irq",
mips_cpu_irq_startup,
mips_cpu_irq_shutdown,
mips_cpu_irq_enable,
mips_cpu_irq_disable,
mips_cpu_irq_ack,
mips_cpu_irq_end,
NULL /* no affinity stuff for UP */
};
void
mips_cpu_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< irq_base+8; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &mips_cpu_irq_controller;
}
mips_cpu_irq_base = irq_base;
}
--- NEW FILE: irq_korva.c ---
/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* This file define the irq handler for MIPS CPU interrupts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* This file exports one global function:
* korva_irq_init(u32 irq_base);
*/
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/korva.h>
#include <asm/mipsregs.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
#include <asm/ddb5xxx/debug.h>
#define NUM_KORVA_IRQS 5
static int korva_irq_base=-1;
static void
korva_irq_enable(unsigned int irq)
{
MIPS_ASSERT(korva_irq_base != -1);
MIPS_ASSERT(irq >= korva_irq_base);
MIPS_ASSERT(irq < korva_irq_base+NUM_KORVA_IRQS);
irq -= korva_irq_base;
korva_out32(KORVA_S_IMR, korva_in32(KORVA_S_IMR) | (1 << irq) );
}
static void
korva_irq_disable(unsigned int irq)
{
MIPS_ASSERT(korva_irq_base != -1);
MIPS_ASSERT(irq >= korva_irq_base);
MIPS_ASSERT(irq < korva_irq_base+NUM_KORVA_IRQS);
irq -= korva_irq_base;
korva_out32(KORVA_S_IMR, korva_in32(KORVA_S_IMR) & ~(1 << irq) );
}
static unsigned int korva_irq_startup(unsigned int irq)
{
korva_irq_enable(irq);
return 0;
}
#define korva_irq_shutdown korva_irq_disable
/* the intr status register is already cleared when we read it */
#define korva_irq_ack korva_irq_disable
#define korva_irq_end korva_irq_enable
static hw_irq_controller korva_irq_controller = {
"KORVA_irq",
korva_irq_startup,
korva_irq_shutdown,
korva_irq_enable,
korva_irq_disable,
korva_irq_ack,
korva_irq_end,
NULL /* no affinity stuff for UP */
};
void
korva_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< irq_base+NUM_KORVA_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &korva_irq_controller;
}
korva_irq_base = irq_base;
}
--- NEW FILE: prom.c ---
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* arch/mips/korva/prom.c
* prom setup file for korva
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
#include <linux/init.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/korva.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
void __init prom_init(void)
{
u32 sdtsr;
u32 ramsize;
strcpy(arcs_cmdline, "console=ttyS0,115200");
strcat(arcs_cmdline, " ip=bootp");
mips_machgroup = MACH_GROUP_NEC_VR41XX;
mips_machtype = MACH_NEC_KORVA;
/* bit 8:9 determines the RAM size */
sdtsr = korva_in32(KORVA_SDTSR);
ramsize = 2 << (1 + ((sdtsr >> 8) & 3));
printk("Korva board with %d MB system RAM\n", ramsize);
add_memory_region(0, ramsize << 20 , BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
--- NEW FILE: reset.c ---
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
void nec_korva_restart(char *command)
{
set_cp0_status(ST0_BEV | ST0_ERL);
change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
flush_cache_all();
write_32bit_cp0_register(CP0_WIRED, 0);
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}
void nec_korva_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1);
}
void nec_korva_power_off(void)
{
nec_korva_halt();
}
--- NEW FILE: setup.c ---
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* arch/mips/korva/setup.c
* The setup file for korva.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/serial.h>
#include <linux/types.h>
#include <linux/string.h> /* for memset */
#include <asm/reboot.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/korva.h>
#include <asm/ddb5xxx/debug.h>
// #define USE_CPU_TIMER 1 /* are we using cpu counter as timer */
extern void nec_korva_restart(char* c);
extern void nec_korva_halt(void);
extern void nec_korva_power_off(void);
static void __init init_serial_ports(void)
{
struct serial_struct s;
/* clear memory */
memset(&s, 0, sizeof(s));
s.line = 0; /* we set the first one */
s.baud_base = 1152000;
// s.irq = 6;
s.irq = 10;
s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
s.iomem_base = (u8*)(KORVA_BASE_VIRT + KORVA_UARTDLL);
s.iomem_reg_shift = 2;
s.io_type = SERIAL_IO_MEM;
MIPS_VERIFY(early_serial_setup(&s), == 0);
}
static void __init nec_korva_time_init(void)
{
/* 100 (CPU clock) MHz divided by 8 */
mips_counter_frequency = 100000000 / 8;
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init nec_korva_timer_setup(struct irqaction *irq)
{
#if defined(USE_CPU_TIMER)
unsigned int count;
setup_irq(7, irq);
/* to generate the first CPU timer interrupt */
count = read_32bit_cp0_register(CP0_COUNT);
write_32bit_cp0_register(CP0_COMPARE, count + 1000);
#else
setup_irq(8,irq);
korva_out32(KORVA_TM0CSR, 100000000 / HZ); /* CPU clock / HZ */
korva_out32(KORVA_TMMR, 0x1); /* start the timer 0 */
#endif
}
#if defined(CONFIG_BLK_DEV_INITRD)
extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
#endif
#if defined(CONFIG_NEC_CANDY)
/* need to come up with a better way. FIXME */
static u_char ETHER_MAC_ADDR[][6] = {
{0x00, 0x00, 0x4c, 0x80, 0x92, 0xa1},
{0x00, 0x00, 0x4c, 0x80, 0x92, 0xa2}
};
extern int
nec_candy_setup_boot_param(uint irq, ulong base_addr, ulong pmd_addr, u_char *mac_addr);
#endif
void __init nec_korva_setup(void)
{
MIPS_DEBUG(printk("nec_korva_setup() starts.\n"));
#if defined(CONFIG_BLK_DEV_INITRD)
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
initrd_start = (unsigned long)&__rd_start;
initrd_end = (unsigned long)&__rd_end;
#endif
board_time_init = nec_korva_time_init;
board_timer_setup = nec_korva_timer_setup;
_machine_restart = nec_korva_restart;
_machine_halt = nec_korva_halt;
_machine_power_off = nec_korva_power_off;
init_serial_ports();
#if defined(CONFIG_NEC_CANDY)
/* setup ether driver */
nec_candy_setup_boot_param(4, 0xb0002000, 0x14, ETHER_MAC_ADDR[0]);
nec_candy_setup_boot_param(5, 0xb0003000, 0x16, ETHER_MAC_ADDR[1]);
#endif
/* ---------------- board hardware setup ---------------- */
/* reset all peripherials, except uart */
// korva_out32(KORVA_S_WRCR, 0x1f);
korva_out32(KORVA_S_WRCR, 0x0f);
/* enable IBUS arbitration for peripherals */
korva_set_bits(KORVA_S_GMR, 0x2);
}
|
|
From: Jun S. <ju...@us...> - 2001-08-23 19:14:00
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv27423/arch/mips
Modified Files:
config.in Makefile
Log Message:
Support NEC Korva board (vr4120a based).
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.15
retrieving revision 1.16
diff -C2 -d -r1.15 -r1.16
*** config.in 2001/08/20 16:09:51 1.15
--- config.in 2001/08/23 19:13:56 1.16
***************
*** 27,30 ****
--- 27,31 ----
int ' Memory size' CONFIG_NEC_EAGLE_MEM_SIZE 32
fi
+ bool 'Support for NEC Korva board (EXPERIMENTAL)' CONFIG_NEC_KORVA
bool 'Support for Galileo EV96100 Evaluation board' CONFIG_MIPS_EV96100
bool 'Support for Galileo EV64120 Evaluation board' CONFIG_MIPS_EV64120
***************
*** 207,210 ****
--- 208,218 ----
define_bool CONFIG_PCI y
fi
+ if [ "$CONFIG_NEC_KORVA" = "y" ]; then
+ define_bool CONFIG_CPU_VR41XX y
+ define_bool CONFIG_SERIAL y
+ define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_SCSI n
+ fi
if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
define_bool CONFIG_PCI y
***************
*** 270,274 ****
"R3000 CONFIG_CPU_R3000 \
R6000 CONFIG_CPU_R6000 \
! R41xx CONFIG_CPU_VR41XX \
R4300 CONFIG_CPU_R4300 \
R4x00 CONFIG_CPU_R4X00 \
--- 278,282 ----
"R3000 CONFIG_CPU_R3000 \
R6000 CONFIG_CPU_R6000 \
! VR41xx CONFIG_CPU_VR41XX \
R4300 CONFIG_CPU_R4300 \
R4x00 CONFIG_CPU_R4X00 \
***************
*** 289,293 ****
bool ' Writeback Buffer available' CONFIG_CPU_HAS_WB
else
! if [ "$CONFIG_CPU_R3000" = "y" -o
"$CONFIG_CPU_VR41XX" = "y" ]; then
if [ "$CONFIG_DECSTATION" = "y" ]; then
--- 297,301 ----
bool ' Writeback Buffer available' CONFIG_CPU_HAS_WB
else
! if [ "$CONFIG_CPU_R3000" = "y" -o \
"$CONFIG_CPU_VR41XX" = "y" ]; then
if [ "$CONFIG_DECSTATION" = "y" ]; then
***************
*** 320,324 ****
"$CONFIG_DDB5476" = "y" -o \
"$CONFIG_NINO" = "y" -o \
! "$CONFIG_NEC_OSPREY" = "y" ]; then
define_bool CONFIG_CPU_LITTLE_ENDIAN y
else
--- 328,333 ----
"$CONFIG_DDB5476" = "y" -o \
"$CONFIG_NINO" = "y" -o \
! "$CONFIG_NEC_OSPREY" = "y" -o \
! "$CONFIG_NEC_KORVA" = "y" ]; then
define_bool CONFIG_CPU_LITTLE_ENDIAN y
else
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.12
retrieving revision 1.13
diff -C2 -d -r1.12 -r1.13
*** Makefile 2001/08/16 16:56:30 1.12
--- Makefile 2001/08/23 19:13:56 1.13
***************
*** 223,226 ****
--- 223,235 ----
#
+ # NEC Korva (vr4120a) board
+ #
+ ifdef CONFIG_NEC_KORVA
+ SUBDIRS += arch/mips/korva
+ LIBS += arch/mips/korva/korva.a
+ LOADADDR += 0x80014000
+ endif
+
+ #
# Galileo EV64120 Board
#
|
|
From: Jun S. <ju...@us...> - 2001-08-23 19:13:59
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv27423/include/asm-mips
Modified Files:
bootinfo.h
Added Files:
korva.h
Log Message:
Support NEC Korva board (vr4120a based).
--- NEW FILE: korva.h ---
/*
* Based on "Preliminary User's Manual: uPD98501 Communication Controller",
* Document No. S14767EJ1V0UM00 (1st edition)
* Date Published April 2000 N CP(K)
*/
#ifndef _korva_h_
#define _korva_h_
/************************************************************************
* ATM
************************************************************************
*/
#define KORVA_A_GMRdefine KORVA_A_GMR 0xF000 /* R/W General Mode Register */
#define KORVA_A_GSR 0xF004 /* R General Status Register */
#define KORVA_A_IMR 0xF008 /* R/W Interrupt Mask Register */
#define KORVA_A_RQU 0xF00C /* R Receive Queue Underrunning */
#define KORVA_A_RQA 0xF010 /* R Receive Queue Alert */
/* ATM F014H - N/A - Reserved for future use */
#define KORVA_A_VER 0xF018 /* R Version Number */
/* ATM F01CH - N/A - Reserved for future use */
#define KORVA_A_CMR 0xF020 /* R/W Command Register */
/* ATM F024H - N/A - Reserved for future use */
#define KORVA_A_CER 0xF028 /* R/W Command Extension Register */
/* ATM F02CH-F04CH - N/A - Reserved for future use */
#define KORVA_A_MSA0 0xF050 /* R/W Mailbox0 Start Address */
#define KORVA_A_MSA1 0xF054 /* R/W Mailbox1 Start Address */
#define KORVA_A_MSA2 0xF058 /* R/W Mailbox2 Start Address */
#define KORVA_A_MSA3 0xF05C /* R/W Mailbox3 Start Address */
#define KORVA_A_MBA0 0xF060 /* R/W Mailbox0 Bottom Address */
#define KORVA_A_MBA1 0xF064 /* R/W Mailbox1 Bottom Address */
#define KORVA_A_MBA2 0xF068 /* R/W Mailbox2 Bottom Address */
#define KORVA_A_MBA3 0xF06C /* R/W Mailbox3 Bottom Address */
#define KORVA_A_MTA0 0xF070 /* R/W Mailbox0 Tail Address */
#define KORVA_A_MTA1 0xF074 /* R/W Mailbox1 Tail Address */
#define KORVA_A_MTA2 0xF078 /* R/W Mailbox2 Tail Address */
#define KORVA_A_MTA3 0xF07C /* R/W Mailbox3 Tail Address */
#define KORVA_A_MWA0 0xF080 /* R/W Mailbox0 Write Address */
#define KORVA_A_MWA1 0xF084 /* R/W Mailbox1 Write Address */
#define KORVA_A_MWA2 0xF088 /* R/W Mailbox2 Write Address */
#define KORVA_A_MWA3 0xF08C /* R/W Mailbox3 Write Address */
#define KORVA_A_RCC 0xF090 /* R Valid Receiving Cell Counter */
#define KORVA_A_TCC 0xF094 /* R Valid Transmitting Cell Counter */
#define KORVA_A_RUEC 0xF098 /* R Receive Unprovisioned VPI/VCI Error Cell Counter */
#define KORVA_A_RIDC 0xF09C /* R Receiving Internal Discarded Cell Counter */
/* ATM F0A0H-F0AFH - N/A - Reserved for future use */
/* ATM F0B0H-F0B3H 4 A_APR R/W ABR Parameter Register */
/* ATM F0B4H-F0BCH - N/A - Reserved for future use */
#define KORVA_A_T1R 0xF0C0 /* R/W T1 Timer Register */
/* ATM F0C4H - N/A - Reserved for future use */
#define KORVA_A_TSR 0xF0C8 /* R/W Time Stamp Register */
/* ATM F200H-F2FFH - N/A - Can not access from VR4120A RISC Core. */
#define KORVA_A_IBBAR 0xF300 /* R/W IBUS Base Address Register */
#define KORVA_A_INBAR 0xF304 /* R/W Instruction Base Address Register */
/* ATM F308H- F31FH - N/A - Reserved for future use */
#define KORVA_A_UMCMD 0xF320 /* R/W UTOPIA Management Interface Command Register */
/* ATM F324H- F3FFH - N/A - Reserved for future use */
/* ATM F400H-F4FFH - N/A - Can not access from VR4120A RISC Core. */
/* ATM F500H-FFFFH - N/A - Reserved for future use */
/************************************************************************
* Ether
************************************************************************
*/
#define KORVA_En_MACC1 0x00 /* R/W MAC configuration register 1 */
#define KORVA_En_MACC2 0x04 /* R/W MAC configuration register 2 */
#define KORVA_En_IPGT 0x08 /* R/W Back-to-Back IPG register */
#define KORVA_En_IPGR 0x0C /* R/W Non Back-to-Back IPG register */
#define KORVA_En_CLRT 0x10 /* R/W Collision register */
#define KORVA_En_LMAX 0x14 /* R/W Max packet length register */
/* Ether 18H-1CH - N/A - Reserved for future use */
#define KORVA_En_RETX 0x20 /* R/W Retry count register */
/* Ether 24H-50H - N/A - Reserved for future use */
#define KORVA_En_LSA2 0x54 /* R/W Station Address register 2 */
#define KORVA_En_LSA1 0x58 /* R/W Station Address register 1 */
#define KORVA_En_PTVR 0x5C /* R Pause timer value read register */
/* Ether 60H - N/A - Reserved for future use */
#define KORVA_En_VLTP 0x64 /* R/W VLAN type register */
#define KORVA_En_MIIC 0x80 /* R/W MII configuration register */
/* Ether 84H-90H - N/A - Reserved for future use */
#define KORVA_En_MCMD 0x94 /* W MII command register */
#define KORVA_En_MADR 0x98 /* R/W MII address register */
#define KORVA_En_MWTD 0x9C /* R/W MII write data register */
#define KORVA_En_MRDD 0xA0 /* R MII read data register */
#define KORVA_En_MIND 0xA4 /* R MII indicator register */
/* Ether A8H-C4H - N/A - Reserved for future use */
#define KORVA_En_HT1 0xCC /* R/W Hash table register 1 */
#define KORVA_En_HT2 0xD0 /* R/W Hash table register 2 */
/* Ether D4H-D8H - N/A - Reserved for future use */
#define KORVA_En_CAR1 0xDC /* R/W Carry register 1 */
#define KORVA_En_CAR2 0xE0 /* R/W Carry register 2 */
/* Ether E4H-12CH - N/A - Reserved for future use */
#define KORVA_En_CAM1 0x130 /* R/W Carry mask register 1 */
#define KORVA_En_CAM2 0x134 /* R/W Carry mask register 2 */
/* Ether 138H-13CH - N/A - Reserved for future use */
#define KORVA_En_RBYT 0x140 /* R/W Receive Byte Counter */
#define KORVA_En_RPKT 0x144 /* R/W Receive Packet Counter */
#define KORVA_En_RFCS 0x148 /* R/W Receive FCS Error Counter */
#define KORVA_En_RMCA 0x14C /* R/W Receive Multicast Packet Counter */
#define KORVA_En_RBCA 0x150 /* R/W Receive Broadcast Packet Counter */
#define KORVA_En_RXCF 0x154 /* R/W Receive Control Frame Packet Counter */
#define KORVA_En_RXPF 0x158 /* R/W Receive PAUSE Frame Packet Counter */
#define KORVA_En_RXUO 0x15C /* R/W Receive Unknown OP code Counter */
#define KORVA_En_RALN 0x160 /* R/W Receive Alignment Error Counter */
#define KORVA_En_RFLR 0x164 /* R/W Receive Frame Length Out of Range Counter */
#define KORVA_En_RCDE 0x168 /* R/W Receive Code Error Counter */
#define KORVA_En_RFCR 0x16C /* R/W Receive False Carrier Counter */
#define KORVA_En_RUND 0x170 /* R/W Receive Undersize Packet Counter */
#define KORVA_En_ROVR 0x174 /* R/W Receive Oversize Packet Counter */
#define KORVA_En_RFRG 0x178 /* R/W Receive Error Undersize Packet Counter */
#define KORVA_En_RJBR 0x17C /* R/W Receive Error Oversize Packet Counter */
#define KORVA_En_R64 0x180 /* R/W Receive 64 Byte Frame Counter */
#define KORVA_En_R127 0x184 /* R/W Receive 65 to 127 Byte Frame Counter */
#define KORVA_En_R255 0x188 /* R/W Receive 128 to 255 Byte Frame Counter */
#define KORVA_En_R511 0x18C /* R/W Receive 256 to 511 Byte Frame Counter */
#define KORVA_En_R1K 0x190 /* R/W Receive 512 to 1023 Byte Frame Counter */
#define KORVA_En_RMAX 0x194 /* R/W Receive Over 1023 Byte Frame Counter */
#define KORVA_En_RVBT 0x198 /* R/W Receive Valid Byte Counter */
#define KORVA_En_TBYT 0x1C0 /* R/W Transmit Byte Counter */
#define KORVA_En_TPCT 0x1C4 /* R/W Transmit Packet Counter */
#define KORVA_En_TFCS 0x1C8 /* R/W Transmit CRC Error Packet Counter */
#define KORVA_En_TMCA 0x1CC /* R/W Transmit Multicast Packet Counter */
#define KORVA_En_TBCA 0x1D0 /* R/W Transmit Broadcast Packet Counter */
#define KORVA_En_TUCA 0x1D4 /* R/W Transmit Unicast Packet Counter */
#define KORVA_En_TXPF 0x1D8 /* R/W Transmit PAUSE control Frame Counter */
#define KORVA_En_TDFR 0x1DC /* R/W Transmit Single Deferral Packet Counter */
#define KORVA_En_TXDF 0x1E0 /* R/W Transmit Excessive Deferral Packet Counter */
#define KORVA_En_TSCL 0x1E4 /* R/W Transmit Single Collision Packet Counter */
#define KORVA_En_TMCL 0x1E8 /* R/W Transmit Multiple collision Packet Counter */
#define KORVA_En_TLCL 0x1EC /* R/W Transmit Late Collision Packet Counter */
#define KORVA_En_TXCL 0x1F0 /* R/W Transmit Excessive Collision Packet Counter */
#define KORVA_En_TNCL 0x1F4 /* R/W Transmit Total Collision Counter */
#define KORVA_En_TCSE 0x1F8 /* R/W Transmit Carrier Sense Error Counter */
#define KORVA_En_TIME 0x1FC /* R/W Transmit Internal MAC Error Counter */
#define KORVA_En_TXCR 0x200 /* R/W Transmit Configuration Register */
#define KORVA_En_TXFCR 0x204 /* R/W Transmit FIFO Control Register */
#define KORVA_En_TXDTR 0x208 /* W Transmit Data Register */
#define KORVA_En_TXSR 0x20C /* R Transmit Status Register */
/* Ether 210H 4 N/A - Reserved for future use */
#define KORVA_En_TXDPR 0x214 /* R/W Transmit Descriptor Register */
#define KORVA_En_RXCR 0x218 /* R/W Receive Configuration Register */
#define KORVA_En_RXFCR 0x21C /* R/W Receive FIFO Control Register */
#define KORVA_En_RXDTR 0x220 /* R Receive Data Register */
#define KORVA_En_RXSR 0x224 /* R Receive Status Register */
/* Ether 228H 4 N/A - Reserved for future use */
#define KORVA_En_RXDPR 0x22C /* R/W Receive Descriptor Register */
#define KORVA_En_RXPDR 0x230 /* R/W Receive Pool Descriptor Register */
/************************************************************************
* SYSCNT
************************************************************************
*/
#define KORVA_S_GMR 0x00 /* R/W General Mode Register */
#define KORVA_S_GSR 0x04 /* R General Status Register */
#define KORVA_S_ISR 0x08 /* RC Interrupt Status Register */
#define KORVA_S_IMR 0x0C /* W Interrupt Mask Register */
#define KORVA_S_NSR 0x10 /* R NMI Status Register */
#define KORVA_S_NMR 0x14 /* R/W NMI Enable Register */
#define KORVA_S_VER 0x18 /* R Version Register */
#define KORVA_S_IOR 0x1C /* R/W IO Port Register */
/* SYSCNT 20H-2FH - N/A - Reserved */
#define KORVA_S_WRCR 0x30 /* W Warm Reset Control Register */
#define KORVA_S_WRSR 0x34 /* R Warm Reset Status Register */
#define KORVA_S_PWCR 0x38 /* W Power Control Register */
#define KORVA_S_PWSR 0x3C /* R Power Control Status Register */
/* SYSCNT 40H-48H - N/A - Reserved */
#define KORVA_S_ITCNTR 0x4C /* R/W IBUS Timeout Timer Control Register */
#define KORVA_S_ITSETR 0x50 /* R/W IBUS Timeout Timer Set Register */
/* SYSCNT 54H-7FH - N/A - Reserved */
#define KORVA_UARTDLL 0x80 /* R/W UART, Divisor Latch LSB Register [DLAB=1] */
#define KORVA_UARTRBR 0x80 /* R UART, Receiver Buffer Register [DLAB=0,READ] */
#define KORVA_UARTTHR 0x80 /* W UART, Transmitter Holding Register [DLAB=0,WRITE] */
#define KORVA_UARTDLM 0x84 /* R/W UART, Divisor Latch MSB Register [DLAB=1] */
#define KORVA_UARTIER 0x84 /* R/W UART, Interrupt Enable Register [DLAB=0] */
#define KORVA_UARTFCR 0x88 /* W UART, FIFO control Register [WRITE] */
#define KORVA_UARTIIR 0x88 /* R UART, Interrupt ID Register [READ] */
#define KORVA_UARTLCR 0x8C /* R/W UART, Line control Register */
#define KORVA_UARTMCR 0x90 /* R/W UART, Modem Control Register */
#define KORVA_UARTLSR 0x94 /* R/W UART, Line status Register */
#define KORVA_UARTMSR 0x98 /* R/W UART, Modem Status Register */
#define KORVA_UARTSCR 0x9C /* R/W UART, Scratch Register */
#define KORVA_DSUCNTR 0xA0 /* R/W DSU Control Register */
#define KORVA_DSUSETR 0xA4 /* R/W DSU Dead Time Set Register */
#define KORVA_DSUCLRR 0xA8 /* W DSU Clear Register */
#define KORVA_DSUTIMR 0xAC /* R/W DSU Elapsed Time Register */
#define KORVA_TMMR 0xB0 /* R/W Timer Mode Register */
#define KORVA_TM0CSR 0xB4 /* R/W Timer CH0 Count Set Register */
#define KORVA_TM1CSR 0xB8 /* R/W Timer CH1 Count Set Register */
#define KORVA_TM0CCR 0xBC /* R Timer CH0 Current Count Register */
#define KORVA_TM1CCR 0xC0 /* R Timer CH1 Current Count Register */
/* SYSCNT C4H-CFH - N/A - Reserved */
#define KORVA_ECCR 0xD0 /* W EEPROMä Command Control Register */
#define KORVA_ERDR 0xD4 /* R EEPROM Read Data Register */
#define KORVA_MACAR1 0xD8 /* R MAC Address Register 1 */
#define KORVA_MACAR2 0xDC /* R MAC Address Register 2 */
#define KORVA_MACAR3 0xE0 /* R MAC Address Register 3 */
/* SYSCNT E4H-FFH - N/A - Reserved */
#define KORVA_RMMDR 0x100 /* R/W Boot ROM Mode Register */
#define KORVA_RMATR 0x104 /* R/W Boot ROM Access Timing Register */
#define KORVA_SDMDR 0x108 /* R/W SDRAM Mode Register */
#define KORVA_SDTSR 0x10C /* R/W SDRAM Type Selection Register */
#define KORVA_SDPTR 0x110 /* R/W SDRAM Precharge Timing Register */
/* #define KORVA_SDRMR 0x114 R/W SDRAM Precharge Mode Register */
/* #define KORVA_SDRCR 0x118 R SDRAM Precharge Timer Count Register */
#define KORVA_SDRMR 0x11C /* R/W SDRAM Refresh Mode Register */
#define KORVA_SDRCR 0x120 /* R SDRAM Refresh Timer Count Register */
#define KORVA_MBCR 0x124 /* R/W Memory Bus Control Register */
/* SYSCNT 128H-FFFH - N/A - Reserved */
/************************************************************************
* USB
************************************************************************
*/
#define KORVA_U_GMR 0x00 /* R/W USB General Mode Register */
#define KORVA_U_VER 0x04 /* R USB Frame number/Version Register */
/* USB 0x08 - N/A R/W Reserved for future use */
/* USB 0x0c - N/A R Reserved for future use */
#define KORVA_U_GSR1 0x10 /* R USB General Status Register 1 */
#define KORVA_U_IMR1 0x14 /* R/W USB Interrupt Mask Register 1 */
#define KORVA_U_GSR2 0x18 /* R USB General Status Resister 2 */
#define KORVA_U_IMR2 0x1c /* R/W USB Interrupt Mask Register 2 */
#define KORVA_U_EP0CR 0x20 /* R/W USB EP0 Control Register */
#define KORVA_U_EP1CR 0x24 /* R/W USB EP1 Control Register */
#define KORVA_U_EP2CR 0x28 /* R/W USB EP2 Control Register */
#define KORVA_U_EP3CR 0x2c /* R/W USB EP3 Control Register */
#define KORVA_U_EP4CR 0x30 /* R/W USB EP4 Control Register */
#define KORVA_U_EP5CR 0x34 /* R/W USB EP5 Control Register */
#define KORVA_U_EP6CR 0x38 /* R/W USB EP6 Control Register */
/* USB 0x3c - N/A - Reserved for future use */
#define KORVA_U_CMR 0x40 /* R/W USB Command Register */
#define KORVA_U_CA 0x44 /* R/W USB Command Address Register */
#define KORVA_U_TEPSR 0x48 /* R/W USB Tx EndPoint Status Register */
/* USB 0x4c - N/A - Reserved for future use */
#define KORVA_U_RP0IR 0x50 /* R/W USB Rx Pool0 Information Register */
#define KORVA_U_RP0AR 0x54 /* R USB Rx Pool0 Address Register */
#define KORVA_U_RP1IR 0x58 /* R/W USB Rx Pool1 Information Register */
#define KORVA_U_RP1AR 0x5c /* R USB Rx Pool1 Address Register */
#define KORVA_U_RP2IR 0x60 /* R/W USB Rx Pool2 Information Register */
#define KORVA_U_RP2AR 0x64 /* R USB Rx Pool2 Address Register */
/* USB 0x68 - N/A - Reserved for future use */
/* USB 0x6c - N/A - Reserved for future use */
#define KORVA_U_TMSA 0x70 /* R/W USB Tx MailBox Start Address Register */
#define KORVA_U_TMBA 0x74 /* R/W USB Tx MailBox Bottom Address Register */
#define KORVA_U_TMRA 0x78 /* R/W USB Tx MailBox Read Address Register */
#define KORVA_U_TMWA 0x7c /* R USB Tx MailBox Write Address Register */
#define KORVA_U_RMSA 0x80 /* R/W USB Rx MailBox Start Address Register */
#define KORVA_U_RMBA 0x84 /* R/W USB Rx MailBox Bottom Address Register */
#define KORVA_U_RMRA 0x88 /* R/W USB Rx MailBox Read Address Register */
#define KORVA_U_RMWA 0x8c /* R USB Rx MailBox Write Address Register */
/* USB 0x90-0xff - N/A - Reserved for future use */
#define KORVA_U_TDN 0x100 /* R USB EP0 Tx Data Phase NAK Counter */
#define KORVA_U_TDS 0x104 /* R USB EP0 Tx Data Phase STALL Counter */
/* USB 0x108 - N/A - Reserved for future use */
/* USB 0x10c - N/A - Reserved for future use */
#define KORVA_U_THT 0x110 /* R USB EP0 Tx Handshake Phase Timeout Counter */
/* USB 0x114 - N/A - Reserved for future use */
/* USB 0x118 - N/A - Reserved for future use */
/* USB 0x11c - N/A - Reserved for future use */
#define KORVA_U_RDT 0x120 /* R USB EP0 Rx Data Phase Timeout Counter */
#define KORVA_U_RDCER 0x124 /* R USB EP0 Rx Data Phase CRC Error Counter */
#define KORVA_U_RDBER 0x128 /* R USB EP0 Rx Data Phase Bitstuff Error Counter */
#define KORVA_U_RDTER 0x12c /* R USB EP0 Rx Data Phase Data Toggle Error Counter */
#define KORVA_U_RHT 0x130 /* R USB EP0 Rx Handshake Phase Timeout Counter */
#define KORVA_U_RHN 0x134 /* R USB EP0 Rx Handshake Phase NAK Counter */
#define KORVA_U_RHS 0x138 /* R USB EP0 Rx Handshake Phase STALL Counter */
/* USB 0x13c - N/A R Reserved for future use */
/* USB 0x140-15f - N/A - Reserved for future use */
#define KORVA_U_DT2 0x160 /* R USB EP2 Data Phase Timeout Counter */
#define KORVA_U_DCER2 0x164 /* R USB EP2 Data Phase CRC Error Counter */
#define KORVA_U_DBER2 0x168 /* R USB EP2 Data Phase Bitstuff Error Counter */
/* USB 0x16c - N/A - Reserved for future use */
/* USB 0x170-17f - N/A - Reserved for future use */
#define KORVA_U_DN3 0x180 /* R USB EP3 Data Phase NAK Counter */
#define KORVA_U_DS3 0x184 /* R USB EP3 Data Phase STALL Counter */
/* USB 0x188 - N/A - Reserved for future use */
/* USB 0x18c - N/A - Reserved for future use */
#define KORVA_U_HT3 0x190 /* R USB EP3 Handshake Phase Timeout Counter */
/* USB 0x194 - N/A - Reserved for future use */
/* USB 0x198 - N/A - Reserved for future use */
/* USB 0x19c - N/A - Reserved for future use */
#define KORVA_U_DT4 0x1a0 /* R USB EP4 Data Phase Timeout Counter */
#define KORVA_U_DCER4 0x1a4 /* R USB EP4 Data Phase CRC Error Counter */
#define KORVA_U_DBER4 0x1a8 /* R USB EP4 Data Phase Bitstuff Error Counter */
#define KORVA_U_DTER4 0x1ac /* R USB EP4 Data Phase Data Toggle Error Counter */
#define KORVA_U_HT4 0x1b0 /* R USB EP4 Handshake Phase Timeout Counter */
#define KORVA_U_HN4 0x1b4 /* R USB EP4 Handshake Phase NAK Counter */
#define KORVA_U_HS4 0x1b8 /* R USB EP4 Handshake Phase STALL Counter */
/* USB 0x1bc - N/A - Reserved for future use */
#define KORVA_U_DN5 0x1c0 /* R USB EP5 Data Phase NAK Counter */
#define KORVA_U_DS5 0x1c4 /* R USB EP5 Data Phase STALL Counter */
/* USB 0x1c8 - N/A - Reserved for future use */
/* USB 0x1cc - N/A - Reserved for future use */
#define KORVA_U_HT5 0x1d0 /* R USB EP5 Handshake Phase Timeout Counter */
/* USB 0x1d4 - N/A - Reserved for future use */
/* USB 0x1d8 - N/A - Reserved for future use */
/* USB 0x1dc - N/A - Reserved for future use */
#define KORVA_U_DT6 0x1e0 /* R USB EP6 Data Phase Timeout Counter */
#define KORVA_U_DCER6 0x1e4 /* R USB EP6 Data Phase CRC Error Counter */
#define KORVA_U_DBER6 0x1e8 /* R USB EP6 Data Phase Bitstuff Error Counter */
#define KORVA_U_DTER6 0x1ec /* R USB EP6 Data Phase Data Toggle Error Counter */
#define KORVA_U_HT6 0x1f0 /* R USB EP6 Handshake Phase Timeout Counter */
#define KORVA_U_HN6 0x1f4 /* R USB EP6 Handshake Phase NAK Counter */
#define KORVA_U_HS6 0x1f8 /* R USB EP6 Handshake Phase STALL Counter */
/* USB 0x1fc - N/A - Reserved for future use */
/************************************************************************
* additional macro
************************************************************************
*/
#define KORVA_BASE 0x10000000
#define KORVA_BASE_VIRT (0xa0000000 + KORVA_BASE)
#ifndef _LANGUAGE_ASSEMBLY
#include <linux/types.h>
#define korva_in32(x) *(volatile u32*)(KORVA_BASE_VIRT + (x))
#define korva_out32(x, y) *(volatile u32*)(KORVA_BASE_VIRT + (x)) = (y)
#define korva_set_bits(x, mask) korva_out32(x, korva_in32(x) | mask)
#define korva_clear_bits(x, mask) korva_out32(x, korva_in32(x) & ~mask)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* _korva_h_ */
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** bootinfo.h 2001/08/16 17:20:36 1.5
--- bootinfo.h 2001/08/23 19:13:56 1.6
***************
*** 202,207 ****
#define MACH_NEC_OSPREY 0 /* Osprey eval board */
#define MACH_NEC_EAGLE 1 /* NEC Eagle board */
! #define GROUP_NEC_VR41XX_NAMES { "Osprey", "Eagle" }
/*
--- 202,208 ----
#define MACH_NEC_OSPREY 0 /* Osprey eval board */
#define MACH_NEC_EAGLE 1 /* NEC Eagle board */
+ #define MACH_NEC_KORVA 2 /* NEC korva board */
! #define GROUP_NEC_VR41XX_NAMES { "Osprey", "Eagle", "Korva" }
/*
|
|
From: Jun S. <ju...@us...> - 2001-08-23 19:13:59
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv27423/arch/mips/kernel
Modified Files:
setup.c proc.c
Log Message:
Support NEC Korva board (vr4120a based).
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** setup.c 2001/08/23 18:32:33 1.8
--- setup.c 2001/08/23 19:13:56 1.9
***************
*** 527,530 ****
--- 527,531 ----
void nec_osprey_setup(void);
void nec_eagle_setup(void);
+ void nec_korva_setup(void);
unsigned long bootmap_size;
***************
*** 619,622 ****
--- 620,628 ----
nec_eagle_setup();
break;
+ #endif
+ #ifdef CONFIG_NEC_KORVA
+ case MACH_GROUP_NEC_VR41XX:
+ nec_korva_setup();
+ break;
#endif
#ifdef CONFIG_MIPS_EV96100
Index: proc.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/proc.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** proc.c 2001/07/16 18:20:36 1.4
--- proc.c 2001/08/23 19:13:56 1.5
***************
*** 51,54 ****
--- 51,55 ----
const char *mach_toshiba_names[] = GROUP_TOSHIBA_NAMES;
const char *mach_alchemy_names[] = GROUP_ALCHEMY_NAMES;
+ const char *mach_nec_vr41xx_names[] = GROUP_NEC_VR41XX_NAMES;
const char **mach_group_to_name[] = { mach_unknown_names,
mach_jazz_names, mach_dec_names, mach_arc_names,
***************
*** 57,61 ****
mach_cosine_names, mach_galileo_names, mach_momenco_names,
mach_ite_names, mach_philips_names, mach_globespan_names,
! mach_sibyte_names, mach_toshiba_names, mach_alchemy_names};
unsigned int version = read_32bit_cp0_register(CP0_PRID);
int len;
--- 58,63 ----
mach_cosine_names, mach_galileo_names, mach_momenco_names,
mach_ite_names, mach_philips_names, mach_globespan_names,
! mach_sibyte_names, mach_toshiba_names, mach_alchemy_names,
! mach_nec_vr41xx_names};
unsigned int version = read_32bit_cp0_register(CP0_PRID);
int len;
|
|
From: Jun S. <ju...@us...> - 2001-08-23 19:13:59
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv27423/drivers/net
Modified Files:
Config.in Makefile
Added Files:
nec_candy.c
Log Message:
Support NEC Korva board (vr4120a based).
--- NEW FILE: nec_candy.c ---
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h> /* get_options(), printk(), panic().. */
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/param.h> /* for HZ */
#include <linux/etherdevice.h> /* init_etherdev() */
#include <linux/if.h>
#include <linux/spinlock.h>
#include <asm/addrspace.h> /* KSEGx() */
#include <asm/irq.h> /* NR_IRQS */
#include <asm/io.h> /* virt_to_phys(), dma_cache_xx() */
/***********************************************************************
* debug
***********************************************************************
*/
[...1926 lines suppressed...]
}
__setup("nec_candy=", nec_candy_boot_setup);
/*
* for module, we have to rely on load time parameters
*
* insmod nec_candy.o irq=<irq1>,<irq2> base_addr=<addr1>,<addr2>
*/
#if defined(MODULE)
MODULE_AUTHOR("Jun Sun, js...@mv... or js...@ju...");
MODULE_DESCRIPTION("Ether driver for NEC Candy controller");
MODULE_PARM_DESC(irq, "IRQ line");
MODULE_PARM(irq, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");
MODULE_PARM_DESC(base_addr, "base address");
MODULE_PARM(base_addr, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");
#endif
#endif
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** Config.in 2001/08/22 18:18:14 1.5
--- Config.in 2001/08/23 19:13:56 1.6
***************
*** 207,210 ****
--- 207,213 ----
tristate ' Baget AMD LANCE support' CONFIG_BAGETLANCE
fi
+ if [ "$CONFIG_NEC_KORVA" = "y" ]; then
+ bool ' NEC Memory-mapped onboard (Candy) Ethernet' CONFIG_NEC_CANDY
+ fi
fi
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Makefile 2001/08/10 03:04:58 1.3
--- Makefile 2001/08/23 19:13:56 1.4
***************
*** 209,212 ****
--- 209,213 ----
obj-$(CONFIG_MAC89x0) += mac89x0.o
obj-$(CONFIG_TUN) += tun.o
+ obj-$(CONFIG_NEC_CANDY) += nec_candy.o
ifeq ($(CONFIG_ARCH_ACORN),y)
|
|
From: Jun S. <ju...@us...> - 2001-08-23 19:08:52
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva In directory usw-pr-cvs1:/tmp/cvs-serv26223/arch/mips/korva Log Message: Directory /cvsroot/linux-mips/linux/arch/mips/korva added to the repository |
|
From: Jun S. <ju...@us...> - 2001-08-23 19:07:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv25674/arch/mips/kernel Modified Files: fast-sysmips.S Added Files: sysmips.c Log Message: Fix sysmips(MIPS_ATOMIC_SET, ...) for CPUs without ll/sc instructions. Now vr41xx and R3000 CPUs should work fine without further patch. When the final fix is settled in oss.sgi.com, we will revert to that. Index: fast-sysmips.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/fast-sysmips.S,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** fast-sysmips.S 2001/07/30 17:33:32 1.1 --- fast-sysmips.S 2001/08/23 19:07:28 1.2 *************** *** 25,31 **** --- 25,33 ---- .set noreorder + #if defined(CONFIG_CPU_HAS_LLSC) li t0, MIPS_ATOMIC_SET beq a0, t0, 1f nop + #endif j sys_sysmips nop |
|
From: James S. <jsi...@us...> - 2001-08-23 18:32:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv15915
Modified Files:
setup.c
Log Message:
Set __rd_start and __rd_end only if we actually have a ramdisk image.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** setup.c 2001/08/17 22:53:26 1.7
--- setup.c 2001/08/23 18:32:33 1.8
***************
*** 743,748 ****
/* Board specific code should have set up initrd_start and initrd_end */
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
! initrd_start = (unsigned long)&__rd_start;
! initrd_end = (unsigned long)&__rd_end;
initrd_below_start_ok = 1;
if (initrd_start) {
--- 743,750 ----
/* Board specific code should have set up initrd_start and initrd_end */
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
! if( __rd_start != __rd_end ) {
! initrd_start = (unsigned long)&__rd_start;
! initrd_end = (unsigned long)&__rd_end;
! }
initrd_below_start_ok = 1;
if (initrd_start) {
|
|
From: Steve L. <slo...@us...> - 2001-08-23 17:20:06
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000 In directory usw-pr-cvs1:/tmp/cvs-serv27157/arch/mips/au1000/pb1000 Modified Files: setup.c Log Message: The #ifdef CONFIG_USB_OHCI was in the wrong place - prevented USB device clock from being enabled. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/pb1000/setup.c,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** setup.c 2001/08/17 22:53:26 1.3 --- setup.c 2001/08/23 17:20:04 1.4 *************** *** 130,138 **** #endif - #ifdef CONFIG_USB_OHCI - outl(usb_clocks, CLOCK_SOURCE_CNTRL); udelay(1000); // enable host controller and wait for reset done outl(0x08, USB_HOST_CONFIG); --- 130,137 ---- #endif outl(usb_clocks, CLOCK_SOURCE_CNTRL); udelay(1000); + #ifdef CONFIG_USB_OHCI // enable host controller and wait for reset done outl(0x08, USB_HOST_CONFIG); |
|
From: Steve L. <slo...@us...> - 2001-08-23 17:10:46
|
Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv24086/drivers/sound
Modified Files:
au1000.c
Log Message:
Renamed the Au1000 dma functions to not collide with kernel/dma.c.
Also, /proc/dma will show the output from kernel/dma.c:get_dma_list(),
not the Au1000 dma list. To fix requires a change to fs/proc/proc_misc.c.
Index: au1000.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/au1000.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** au1000.c 2001/08/17 22:53:26 1.1
--- au1000.c 2001/08/23 17:10:44 1.2
***************
*** 500,504 ****
#ifdef AU1000_VERBOSE_DEBUG
! dump_dma_channel(db->dmanr);
#endif
--- 500,504 ----
#ifdef AU1000_VERBOSE_DEBUG
! dump_au1000_dma_channel(db->dmanr);
#endif
***************
*** 537,541 ****
#ifdef AU1000_VERBOSE_DEBUG
! dump_dma_channel(db->dmanr);
#endif
--- 537,541 ----
#ifdef AU1000_VERBOSE_DEBUG
! dump_au1000_dma_channel(db->dmanr);
#endif
***************
*** 1889,1897 ****
// Allocate the DMA Channels
! if ((s->dma_dac.dmanr = request_dma(DMA_ID_AC97C_TX, "audio DAC")) < 0) {
err("Can't get DAC DMA");
goto err_dma1;
}
! if ((s->dma_adc.dmanr = request_dma(DMA_ID_AC97C_RX, "audio ADC")) < 0) {
err("Can't get ADC DMA");
goto err_dma2;
--- 1889,1899 ----
// Allocate the DMA Channels
! if ((s->dma_dac.dmanr = request_au1000_dma(DMA_ID_AC97C_TX,
! "audio DAC")) < 0) {
err("Can't get DAC DMA");
goto err_dma1;
}
! if ((s->dma_adc.dmanr = request_au1000_dma(DMA_ID_AC97C_RX,
! "audio ADC")) < 0) {
err("Can't get ADC DMA");
goto err_dma2;
***************
*** 1991,1997 ****
unregister_sound_dsp(s->dev_audio);
err_dev1:
! free_dma(s->dma_adc.dmanr);
err_dma2:
! free_dma(s->dma_dac.dmanr);
err_dma1:
free_irq(s->dma_adc.irq, s);
--- 1993,1999 ----
unregister_sound_dsp(s->dev_audio);
err_dev1:
! free_au1000_dma(s->dma_adc.dmanr);
err_dma2:
! free_au1000_dma(s->dma_dac.dmanr);
err_dma1:
free_irq(s->dma_adc.irq, s);
***************
*** 2016,2021 ****
free_irq(s->dma_adc.irq, s);
free_irq(s->dma_dac.irq, s);
! free_dma(s->dma_adc.dmanr);
! free_dma(s->dma_dac.dmanr);
release_region(virt_to_phys((void*)AC97C_CONFIG), 0x14);
unregister_sound_dsp(s->dev_audio);
--- 2018,2023 ----
free_irq(s->dma_adc.irq, s);
free_irq(s->dma_dac.irq, s);
! free_au1000_dma(s->dma_adc.dmanr);
! free_au1000_dma(s->dma_dac.dmanr);
release_region(virt_to_phys((void*)AC97C_CONFIG), 0x14);
unregister_sound_dsp(s->dev_audio);
|
582 messages has been excluded from this view by a project administrator.
