From: Ville <sy...@sc...> - 2005-10-29 11:29:00
|
On Fri, Oct 28, 2005 at 10:18:36PM +0200, Geert Uytterhoeven wrote: > On Fri, 28 Oct 2005, coutal coutal wrote: > > i am using the atyfb driver on my powermac 5500 (ati rage II 215GT). = after > > upgrading the kernel, three vertical bands of visible distortion appe= ared in > > my console. they are not videomode-tied (tried almost all my card sup= ports) > > and thus i suspect some breakage in the driver. >=20 > Which kernel version worked fine? Which one caused the regression? >=20 > > can anyone please have a look at it? > > moreover, what could cause such an effect? would it be memory clock o= r pll > > programming? please enlighten me a bit, i am curious. >=20 > This looks more like a problem with the display FIFO programming (DSP_* > registers): some RAGE chips have 24 entries in the display FIFO, others= have > 32. One thing that sticks out is dsp_loop_latency. This patch changes the=20 calculation to be more like the old way. It's still a bit different since= =20 the new code takes more memory types into consideration. Completely=20 untested on any hardware... --- mach64_ct.c.orig 2005-10-29 14:05:40.000000000 +0300 +++ mach64_ct.c 2005-10-29 14:10:37.000000000 +0300 @@ -425,8 +425,10 @@ =20 if (M64_HAS(FIFO_32)) { pll->ct.fifo_size =3D 32; + pll->ct.dsp_loop_latency =3D 2; } else { pll->ct.fifo_size =3D 24; + pll->ct.dsp_loop_latency =3D 0; pll->ct.xclkpagefaultdelay +=3D 2; pll->ct.xclkmaxrasdelay +=3D 3; } @@ -434,35 +436,35 @@ switch (par->ram_type) { case DRAM: if (info->fix.smem_len<=3DONE_MB) { - pll->ct.dsp_loop_latency =3D 10; + pll->ct.dsp_loop_latency +=3D 8; } else { - pll->ct.dsp_loop_latency =3D 8; + pll->ct.dsp_loop_latency +=3D 6; pll->ct.xclkpagefaultdelay +=3D 2; } break; case EDO: case PSEUDO_EDO: if (info->fix.smem_len<=3DONE_MB) { - pll->ct.dsp_loop_latency =3D 9; + pll->ct.dsp_loop_latency +=3D 7; } else { - pll->ct.dsp_loop_latency =3D 8; + pll->ct.dsp_loop_latency +=3D 6; pll->ct.xclkpagefaultdelay +=3D 1; } break; case SDRAM: if (info->fix.smem_len<=3DONE_MB) { - pll->ct.dsp_loop_latency =3D 11; + pll->ct.dsp_loop_latency +=3D 9; } else { - pll->ct.dsp_loop_latency =3D 10; + pll->ct.dsp_loop_latency +=3D 8; pll->ct.xclkpagefaultdelay +=3D 1; } break; case SGRAM: - pll->ct.dsp_loop_latency =3D 8; + pll->ct.dsp_loop_latency +=3D 6; pll->ct.xclkpagefaultdelay +=3D 3; break; default: - pll->ct.dsp_loop_latency =3D 11; + pll->ct.dsp_loop_latency +=3D 9; pll->ct.xclkpagefaultdelay +=3D 3; break; } --=20 Ville Syrj=E4l=E4 sy...@sc... http://www.sci.fi/~syrjala/ |