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Re: usb1.1 vs libusb-1.0.9
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From: Tim R. <ti...@pr...> - 2012-11-14 18:22:18
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geo wrote: > The endpoints are filled on the USB TX ISR with EP transfer re-enabled at the end of isr. Does the USB TX interrupt happen when the FIFO goes empty? I presume it does. Is there some reason you haven't told us what microcontroller you are using, despite three requests? > Too bad I do not have access to an USB analyzer ... > I tried to measure the USB TX ISR length ... > Here is what I got with a logic analyzer and gpio debug ... > > 10.63us 10.63us > __________ __________ > | | | | > ^ | ^ | > | | | | > _______________| |_____________________________| |______ > | | > A B > > figure looks good on plain editor ... sorry for the mess > > The USB TX ISR is always 10.63us, less than 20us ... Even so, you understand that your device cannot use the bus during this period, right? Under the best possible conditions, you will never be able to achieve more than 66% duty cycle (20us to transfer, 10us to refill). That immediately cuts 1/3 from your maximum bandwidth. > The distance between the rising edges ( distance between points A and B in the figure ) is always > one of these 3 values: 73us, 52us, 113us > I do not understand the source of this variation ... It may be a host controller thing. Think about it this way. After you finish a transmission, the host controller is going to send you another IN token to start the next block. If you happen to be busy servicing your interrupt, your microcontroller will NAK that request (presumably). It is then up to the host controller to retry the request later, but there's nothing in the spec that says how long "later" is. -- Tim Roberts, ti...@pr... Providenza & Boekelheide, Inc. |
