Re: [Libusb-devel] libusb_bulk_transfer timeout (Win7 x64)

[michele.paolino <mic...@st...>]

My problem was solved by writing a new FX2 firmware. In particular, I was
inspired by FX2 examples firmware (Bulk-src) installed automatically with
Cypress tools.
Thank you to all, specially to Tim, for your advices.
Regards

On Wed, Jan 18, 2012 at 7:21 PM, Tim Roberts <ti...@pr...> wrote:

> michele.paolino wrote:
> >
> > I want to use FX2 to send and reveive packets between Pc and FPGA. For
> > test purposes I think that also loopback could be fine. I understood
> > that Auto mode give the possibility to send/receive packets
> > automatically, without the firmware aid...but clearly I'm wrong. So
> > I'll take a look to my firmware.
>
> No, it's not THAT automatic.  Each endpoint has a FIFO.  For an IN
> endpoint (device-to-host), somebody has to shove data into that FIFO.
> The FX2's USB engine will not send a packet out from a FIFO until the
> packet is "committed".  Until then, the data just sits in the FIFO.
> What "auto" mode does is say "as soon as there are N bytes of data in
> the FIFO, it should automatically be committed."
>
> Each endpoint has its own completely separate FIFO.  The data you are
> getting on your OUT endpoint (host-to-device) is going into a separate
> area of memory than the data you are sending on your IN endpoint.  To do
> loopback, someone, somewhere has to copy that data.  I thought Cypress
> has some sample firmware in their development kit that did that.
>
> If you already have your hardware with your FPGA attached, it might be
> easier to write a little Verilog to do the copying.  That would also let
> you check your slave mode handling.  Remember that the CPU in the FX2 is
> unbelievably slow -- at the maximum clock rate, it runs 3 or 4 MIPS.
> Copying 512 bytes requires half a millisecond, which is 4 microframes.
>
> --
> Tim Roberts, ti...@pr...
> Providenza & Boekelheide, Inc.
>
>
>
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-- 
Michele Paolino