It's been a couple of years since anyone has posted here, and it's probably because libieee1284 is working great for everyone!
The library seems as relevant as ever. Here we're interfacing the PC to embedded logic and memory via ieee1284_ecp_read_data.
We use no ieee1284 negotiate, read device id, or negotiate channel forward to reverse.
We just open the port, claim it and call the ecp read data.
This does work! Our FPGA provides the data to the parallel port and into the application with minimal verilog required.
This is far from ieee1284 compliant, but it gets the data into the PC, and that's all that really matters in this case.
The only disappointing thing is the transfer rate. We'd like to get around 1Mbyte/sec but we're only getting 100Kbyte/sec 8-(
When ieee1284_ecp_read_data is called with size_t counts greater than 1024, it only reads 1024 bytes. This 1Kbyte transfer takes almost exactly 10ms. Yielding the 100Kbyte/sec transfer rate.
Now for the questions:
Is there some way to make ecp_read_data provide more data per block? How much?
Any ideas on how to get the transfer rate up by an order of magnitude?
Are we loosing the higher transfer rates by not going through the whole ECP negotiation business?
This is the output of the transfer test:
sizeof\(size\_t\)=4
Finding ports...1 port found
Opening parport0...base addr=0x378 capabilities=0x18EF
Supported modes: RAW NIBBLE BYTE COMPAT ECP ECPRLE ECPSWE IRQ DMA
ieee1284\_ecp\_read\_data: len=49152
Read transfered 1024 bytes
For the embedded system design work here, the parallel port is the easiest way to get a decent data transfer rate from the PC. libieee1284 has made it easy!
Thanks for this great piece of code!!!
johnea
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Hello,
It's been a couple of years since anyone has posted here, and it's probably because libieee1284 is working great for everyone!
The library seems as relevant as ever. Here we're interfacing the PC to embedded logic and memory via ieee1284_ecp_read_data.
We use no ieee1284 negotiate, read device id, or negotiate channel forward to reverse.
We just open the port, claim it and call the ecp read data.
This does work! Our FPGA provides the data to the parallel port and into the application with minimal verilog required.
This is far from ieee1284 compliant, but it gets the data into the PC, and that's all that really matters in this case.
The only disappointing thing is the transfer rate. We'd like to get around 1Mbyte/sec but we're only getting 100Kbyte/sec 8-(
When ieee1284_ecp_read_data is called with size_t counts greater than 1024, it only reads 1024 bytes. This 1Kbyte transfer takes almost exactly 10ms. Yielding the 100Kbyte/sec transfer rate.
Now for the questions:
Is there some way to make ecp_read_data provide more data per block? How much?
Any ideas on how to get the transfer rate up by an order of magnitude?
Are we loosing the higher transfer rates by not going through the whole ECP negotiation business?
This is the output of the transfer test:
For the embedded system design work here, the parallel port is the easiest way to get a decent data transfer rate from the PC. libieee1284 has made it easy!
Thanks for this great piece of code!!!
johnea