[L4alpha-cvscommit] CVS: L4Alpha/pal/21164/macros l4_macros.mar,1.5,1.6

[Daniel P. <dp...@us...>]

Update of /cvsroot/l4alpha/L4Alpha/pal/21164/macros
In directory usw-pr-cvs1:/tmp/cvs-serv4834/pal/21164/macros

Modified Files:
	l4_macros.mar 
Log Message:
Interrupt mask and unmask functionality

When you do a l4_ipc_receive on your registered interrupt, it will enable the interrupt pin to the cpu. When the kernel recieves this and passes it on to you, it will disable (mask) this interrupt and pass it on to you.
This prevents some race conditions that were occuring.

Breaks the Ruffian port.




Index: l4_macros.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/macros/l4_macros.mar,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** l4_macros.mar	7 May 2001 08:36:01 -0000	1.5
--- l4_macros.mar	13 Feb 2002 06:42:07 -0000	1.6
***************
*** 59,64 ****
  ; == Enable Interrupt and Disable Interupt ==
  ;  For code executing un-interrupted in kernel mode.
! .macro enable_int dummy=zero
! 	mtpr	zero, ipl
  	NOP
  	NOP
--- 59,66 ----
  ; == Enable Interrupt and Disable Interupt ==
  ;  For code executing un-interrupted in kernel mode.
! .macro enable_int tmp=AT
!         mfpr	  tmp, tr5
! 	NOP
! 	mtpr	  tmp, ipl
  	NOP
  	NOP
***************
*** 70,73 ****
--- 72,94 ----
  	NOP
          NOP
+ .endm
+ 
+ .macro init_ipl
+        mtpr	zero, tr5	; enables ALL interrupts
+ .endm
+ 
+ ; mask_int - turn off interrupt
+ ; FIXME - this breaks ruffian (broken timer interrupt)
+ .macro mask_int int tmp
+        mfpr	tmp, tr5
+        bis	tmp, int, tmp
+        mtpr	tmp, tr5
+ .endm
+ 
+ ; unmask_int - turn on interrupt
+ .macro unmask_int int tmp
+        mfpr	tmp, tr5
+        bic	tmp, int, tmp
+        mtpr	tmp, tr5
  .endm