[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.21,1.22 memory.mar,1.8,1.9

[Daniel P. <dp...@us...>]

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv32332/pal

Modified Files:
	ipc.mar memory.mar 
Log Message:
(Finally) added support for read-only pages.

Tested on 21264 only. 
WARNING: The 21064 and 21164 updates will come in a later commit.


Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.21
retrieving revision 1.22
diff -C2 -d -r1.21 -r1.22
*** ipc.mar	6 Feb 2002 03:20:17 -0000	1.21
--- ipc.mar	10 Feb 2002 12:37:58 -0000	1.22
***************
*** 1443,1447 ****
  	mov	t1, s0					; Flexpage 0.low
  	mov	t0, s1					; Flexpage 0.hig
! 		
  	push	p_ra
  	tcb_ptr	a0, t1
--- 1443,1447 ----
  	mov	t1, s0					; Flexpage 0.low
  	mov	t0, s1					; Flexpage 0.hig
! 
  	push	p_ra
  	tcb_ptr	a0, t1
***************
*** 1542,1546 ****
  	REPEAT
  		push	p_t2
! 	
  		srl	t6, #2, t4
  		subq	t4, #PAGEBITS, t4
--- 1542,1546 ----
  	REPEAT
  		push	p_t2
! 
  		srl	t6, #2, t4
  		subq	t4, #PAGEBITS, t4
***************
*** 1553,1556 ****
--- 1553,1558 ----
  			
  			srl	s0, #2, t4
+ 			and	s0, #2, a4			; write bit.
+ 
  			subq	t4, #PAGEBITS, t4
  			IFGT	t4
***************
*** 1584,1588 ****
  					push	p_t0!p_t1!p_t3!p_t5!p_t6!p_t7!p_t8
  
- 					
  					push	p_t1
  					push	p_t6
--- 1586,1589 ----
***************
*** 1594,1597 ****
--- 1595,1599 ----
  					bsr	ra, mem_translate_address
  					mov	t7, t2
+ 
  					pop	p_a0
  					pop	p_t1

Index: memory.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/memory.mar,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** memory.mar	5 Feb 2002 06:24:00 -0000	1.8
--- memory.mar	10 Feb 2002 12:37:58 -0000	1.9
***************
*** 329,332 ****
--- 329,336 ----
  		pop	p_t3
  		PVC_JSR mta_protection_miss bsr=1 dest=1
+ 		
+ 		; FIXME - here we have to minipulate prot bits of the PTE in
+                 ;  a1 - or can it be done earlier???
+ 
  		ret	zero, (ra)
  	XENDIF
***************
*** 424,429 ****
  
  ;+------------------------------------------------------------------------------
! ; FUNCTION: mem_map_page
! ;	map a page and enter data into the maptree structure
  ;
  ; MODE: K
--- 428,432 ----
  
  ;+------------------------------------------------------------------------------
! ; FUNCTION: mem_map_page;	map a page and enter data into the maptree structure
  ;
  ; MODE: K
***************
*** 446,453 ****
  	push	p_t2					; Pointer to Source PTE
  	push	p_t1!p_a0!p_a1
  	mov	t1, t0
  	clr	t6
! 	GET_16CONS	a2, 13					; Page size
! 	GET_16CONS	a4, <PP_WRITABLE ! PP_EXECUTABLE>	; Page Attributes CHANGE IT
  	disable_int
  	PVC_JSR mem_insert_pte bsr=1
--- 449,479 ----
  	push	p_t2					; Pointer to Source PTE
  	push	p_t1!p_a0!p_a1
+ 
+ 	; Shift a4 into position the UWE bit is in PTE
+ 	; currently w bit is bit 2
+ 
+ 	GET_16CONS  a2, ^x1
+ 	sll	    a2, #15, a2
+ 	and	    a1, a2, a2		; uwe bit currently on or off?
+ 
+ 	sll	    a4, #<14>, t6 	; new uwe bit <15-1>
+ 	bic	    a1, a2, t0
+ 
+ 	or	    t6, t0, t6
+ 	cmovne	    a2, t6, a1			; test and set UWE in TCB frame data
+ 	
+ 	GET_16CONS	t6, <PP_EXECUTABLE>	; Page Attributes CHANGE IT
+ 
+ 	sll		a4, #6, a4
+ 	or		t6, a4, a4
+ 	cmoveq		a2, t6, a4
+ 
+ 
+ 	GET_16CONS	a2, 13					; Page size
+ 
+ 
  	mov	t1, t0
  	clr	t6
! 
  	disable_int
  	PVC_JSR mem_insert_pte bsr=1
***************
*** 691,695 ****
  	ldq_p	t7, 8(t2)			; t0 = higher part of guard
  
- 
  	xor	t3, t1, t3			; guard bits and flip prot.
  	bic	t7, #^x3f, t2			; t2 = old.frame start base	
--- 717,720 ----
***************
*** 715,734 ****
  	; we should get the pointer and update the (new) permissions
  
! ;	GET_16CONS AT, ^x3ff
! ;	bic	t3, AT, t2
  
  	mov	t8, t9
! ;	bis	t2, #13, t2			; set guard` length
! ;	or	t2, a4, t2
! ;	stq_p	t2, 0(t9)			; kpush new low part
! ;	stq_p	a1, 8(t9)			; Store new high part	
   	clr	a1
  	bis	zero, #1, t10
- 	
- 	; We don't bother flushing entry here, it can be done in TLB fault handler.
  
  	
  	PVC_JSR mem_insert_pte bsr=1 dest=1; 
! 	ret	zero, (ra)			; Entry is always in tabls
  	
  	;+
--- 740,762 ----
  	; we should get the pointer and update the (new) permissions
  
! 	ldq_p   t3, 0(t8)
  
+ 	GET_16CONS AT, ^x3ff
+ 
+ 	bic	t3, AT, t2
  	mov	t8, t9
! 	bis	t2, #13, t2			; set guard` length
! 	or	t2, a4, t2
! 
! 	stq_p	t2, 0(t9)			; kpush new low part
! 	stq_p	a1, 8(t9)			; Store new high part	
   	clr	a1
  	bis	zero, #1, t10
  
+ 	; We don't bother flushing entry here, it can be done in TLB fault
+         ; handler. We flush in the DFAULT handler prior to entering this routine.
  	
  	PVC_JSR mem_insert_pte bsr=1 dest=1; 
! 	ret	zero, (ra)
  	
  	;+
***************
*** 862,865 ****
--- 890,898 ----
  	bis	t2, #13, t2			; set guard` length
  	or	t2, a4, t2
+ 
+ 	khex	t2, 64
+ 	khex	a1, 64
+ 	
+ 
  	stq_p	t2, 0(t9)			; kpush new low part
  	stq_p	a1, 8(t9)			; Store new high part