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[kvm-devel] [5/24] Update vga.c for ia64.
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From: Zhang, X. <xia...@in...> - 2007-12-09 15:55:02
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From: Zhang Xiantao <xia...@in...>
Date: Wed, 5 Dec 2007 10:32:42 +0800
Subject: [PATCH] kvm qemu: Update vga.c for ia64 support.
Since current IA64 doesn't support dirty log, always set
whole screen as dirty. We didn't find performance lose.
In addition, this patch adds vga bios support for ia64, due
to short of vga bios support in ia64/firmware.
Signed-off-by: Zhang Xiantao <xia...@in...>
---
qemu/hw/vga.c | 141
++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 140 insertions(+), 1 deletions(-)
diff --git a/qemu/hw/vga.c b/qemu/hw/vga.c
index 3024ebc..382e488 100644
--- a/qemu/hw/vga.c
+++ b/qemu/hw/vga.c
@@ -1449,13 +1449,17 @@ static void vga_draw_graphic(VGAState *s, int
full_update)
/* HACK ALERT */
#define BITMAP_SIZE ((8*1024*1024) / 4096 / 8 / sizeof(long))
unsigned long bitmap[BITMAP_SIZE];
+#ifndef TARGET_IA64
int r;
-
if (kvm_allowed) {
r =3D kvm_get_dirty_pages(kvm_context, s->map_addr, &bitmap);
if (r < 0)
fprintf(stderr, "kvm: get_dirty_pages returned
%d\n", r);
}
+#else=20
+ memset(bitmap, 0xff, BITMAP_SIZE*sizeof(long));=20
+ //FIXME:Always flush full screen before log dirty ready!!
+#endif
#endif
=20
full_update |=3D update_basic_params(s);
@@ -1868,6 +1872,138 @@ static void vga_map(PCIDevice *pci_dev, int
region_num,
}
}
=20
+#ifdef TARGET_IA64
+/* do the same job as vgabios before vgabios get ready - yeah */
+void vga_bios_init(VGAState *s)
+{
+ uint8_t palette_model[192] =3D {
+ 0, 0, 0, 0, 0, 170, 0, 170,
+ 0, 0, 170, 170, 170, 0, 0, 170,
+ 0, 170, 170, 85, 0, 170, 170, 170,
+ 85, 85, 85, 85, 85, 255, 85, 255,
+ 85, 85, 255, 255, 255, 85, 85, 255,=20
+ 85, 255, 255, 255, 85, 255, 255, 255,
+ 0, 21, 0, 0, 21, 42, 0, 63,
+ 0, 0, 63, 42, 42, 21, 0, 42,
+ 21, 42, 42, 63, 0, 42, 63, 42,
+ 0, 21, 21, 0, 21, 63, 0, 63,=20
+ 21, 0, 63, 63, 42, 21, 21, 42,
+ 21, 63, 42, 63, 21, 42, 63, 63,
+ 21, 0, 0, 21, 0, 42, 21, 42,
+ 0, 21, 42, 42, 63, 0, 0, 63,
+ 0, 42, 63, 42, 0, 63, 42, 42,
+ 21, 0, 21, 21, 0, 63, 21, 42,
+ 21, 21, 42, 63, 63, 0, 21, 63,
+ 0, 63, 63, 42, 21, 63, 42, 63,
+ 21, 21, 0, 21, 21, 42, 21, 63,
+ 0, 21, 63, 42, 63, 21, 0, 63,
+ 21, 42, 63, 63, 0, 63, 63, 42,
+ 21, 21, 21, 21, 21, 63, 21, 63,
+ 21, 21, 63, 63, 63, 21, 21, 63,
+ 21, 63, 63, 63, 21, 63, 63, 63
+ };
+
+ s->latch =3D 0;=20
+
+ s->sr_index =3D 3;=20
+ s->sr[0] =3D 3;
+ s->sr[1] =3D 0;
+ s->sr[2] =3D 3;
+ s->sr[3] =3D 0;
+ s->sr[4] =3D 2;
+ s->sr[5] =3D 0;
+ s->sr[6] =3D 0;
+ s->sr[7] =3D 0;
+
+ s->gr_index =3D 5;=20
+ s->gr[0] =3D 0;
+ s->gr[1] =3D 0;
+ s->gr[2] =3D 0;
+ s->gr[3] =3D 0;
+ s->gr[4] =3D 0;
+ s->gr[5] =3D 16;
+ s->gr[6] =3D 14;
+ s->gr[7] =3D 15;
+ s->gr[8] =3D 255;
+
+ /* changed by out 0x03c0 */
+ s->ar_index =3D 32;
+ s->ar[0] =3D 0;
+ s->ar[1] =3D 1;
+ s->ar[2] =3D 2;
+ s->ar[3] =3D 3;
+ s->ar[4] =3D 4;
+ s->ar[5] =3D 5;
+ s->ar[6] =3D 6;
+ s->ar[7] =3D 7;
+ s->ar[8] =3D 8;
+ s->ar[9] =3D 9;
+ s->ar[10] =3D 10;
+ s->ar[11] =3D 11;
+ s->ar[12] =3D 12;
+ s->ar[13] =3D 13;
+ s->ar[14] =3D 14;
+ s->ar[15] =3D 15;
+ s->ar[16] =3D 12;
+ s->ar[17] =3D 0;
+ s->ar[18] =3D 15;
+ s->ar[19] =3D 8;
+ s->ar[20] =3D 0;
+
+ s->ar_flip_flop =3D 1;=20
+
+ s->cr_index =3D 15;=20
+ s->cr[0] =3D 95;
+ s->cr[1] =3D 79;
+ s->cr[2] =3D 80;
+ s->cr[3] =3D 130;
+ s->cr[4] =3D 85;
+ s->cr[5] =3D 129;
+ s->cr[6] =3D 191;
+ s->cr[7] =3D 31;
+ s->cr[8] =3D 0;
+ s->cr[9] =3D 79;
+ s->cr[10] =3D 14;
+ s->cr[11] =3D 15;
+ s->cr[12] =3D 0;
+ s->cr[13] =3D 0;
+ s->cr[14] =3D 5;
+ s->cr[15] =3D 160;
+ s->cr[16] =3D 156;
+ s->cr[17] =3D 142;
+ s->cr[18] =3D 143;
+ s->cr[19] =3D 40;
+ s->cr[20] =3D 31;
+ s->cr[21] =3D 150;
+ s->cr[22] =3D 185;
+ s->cr[23] =3D 163;
+ s->cr[24] =3D 255;
+
+ s->msr =3D 103;=20
+ s->fcr =3D 0;=20
+ s->st00 =3D 0;=20
+ s->st01 =3D 0;=20
+
+ /* dac_* & palette will be initialized by os through out 0x03c8 &
+ * out 0c03c9(1:3) */
+ s->dac_state =3D 0;=20
+ s->dac_sub_index =3D 0;=20
+ s->dac_read_index =3D 0;=20
+ s->dac_write_index =3D 16;=20
+ s->dac_cache[0] =3D 255;
+ s->dac_cache[1] =3D 255;
+ s->dac_cache[2] =3D 255;
+
+ /* palette */
+ memcpy(s->palette, palette_model, 192);
+
+ s->bank_offset =3D 0;
+ s->graphic_mode =3D -1;
+
+ /* TODO: add vbe support if enabled */
+}
+#endif
+
/* when used on xen/kvm environment, the vga_ram_base is not used */
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t
*vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
@@ -1916,6 +2052,9 @@ void vga_common_init(VGAState *s, DisplayState
*ds, uint8_t *vga_ram_base,
s->update =3D vga_update_display;
s->invalidate =3D vga_invalidate_display;
s->screen_dump =3D vga_screen_dump;
+#ifdef TARGET_IA64
+ vga_bios_init(s);
+#endif
}
=20
/* used by both ISA and PCI */
--=20
1.5.2
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