[Ktechlab-devel] Testing document structure and simulation

[P Z. <zol...@gm...>]

   Hi,

  I'm thinking about a possible way to test the entire circuit simulator.  
We could load in a testbench a well-known circuit and let the simulator  
run it for a few steps. The correct simulation results should be also  
stored and checked against the actual results.
  For this to work, the following functionality is needed:
- load a document/file from a file
- step the simulator, from a program
- ability to collect all the node voltages and branch currents from the  
circuit. As I know, currently this is not implemented.
- load previous results from files

  Opinions? (don't expect the implementation of this soon, but we could  
agree on many aspects).