In clocked JK and D flip-flops the signal levels on J and K or D have no effect until the device is clocked. If the flip-flop changes when the clock rises from 0 to 1 it is called POSITIVE-EDGE TRIGGERED FLIP-FLOP. If the flip-flop changes when the clock signal changes from 1 to 0 it is called NEGATIVE-EDGE TRIGGERED FLIP-FLOP. This is indicated by a small circle at the clock terminal.
With the symbol drawn right now at the integrated circuits in KTechLab, it is supposed that the flip-flops are positive-edge triggered devices, but what really happens is that both of them (JK and D) are negative-edge triggered devices.
I suggest to change the behavior of the devices, or change the symbol of the circuit adding a small circle at the clock terminal...
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