[Kernelloader-cvs] linux/simple-toolchain gcc-svn-20130701-mips-ps2.patch, NONE, 1.1

[Mega M. <kl...@us...>]

Update of /cvsroot/kernelloader/linux/simple-toolchain
In directory sfp-cvs-1.v30.ch3.sourceforge.com:/tmp/cvs-serv8213

Added Files:
	gcc-svn-20130701-mips-ps2.patch 
Log Message:
Update floating point.
The compiler now knows that the FPU is not IEEE 754 compliant.
This can be configured by --with-float=single.
This only works in mipsr5900el toolchain.
Programs can't expect that it behaves like IEEE 754.
The GCC is not able to emulate IEEE 754 at the moment.


--- NEW FILE: gcc-svn-20130701-mips-ps2.patch ---
Index: gcc/real.c
===================================================================
--- gcc/real.c	(Revision 200583)
+++ gcc/real.c	(Arbeitskopie)
@@ -3028,6 +3028,34 @@
     true
   };
 
+/*  r5900 Single precision format is the same as IEEE
+    single precision with the following differences:
+      - Infinities are not supported.  Instead MAX_FLOAT or MIN_FLOAT
+	are generated.
+      - NaNs are not supported.
+      - Denormals are not supported.
+      - the only supported rounding mode is trunction (towards zero).  */
+const struct real_format r5900_single_format =
+  {
+    encode_ieee_single,
+    decode_ieee_single,
+    2,
+    24,
+    24,
+    -125,
+    128,
+    31,
+    31,
+    true,
+    true,
+    false,
+    false,
+    false,
+    true,
+    false,
+    true
+  };
+
 const struct real_format motorola_single_format =
   {
     encode_ieee_single,
Index: gcc/real.h
===================================================================
--- gcc/real.h	(Revision 200583)
+++ gcc/real.h	(Arbeitskopie)
@@ -303,6 +303,7 @@
 /* Target formats defined in real.c.  */
 extern const struct real_format ieee_single_format;
 extern const struct real_format mips_single_format;
+extern const struct real_format r5900_single_format;
 extern const struct real_format motorola_single_format;
 extern const struct real_format spu_single_format;
 extern const struct real_format ieee_double_format;
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc	(Revision 200583)
+++ gcc/config.gcc	(Arbeitskopie)
@@ -3472,7 +3475,7 @@
 		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt synci"
 
 		case ${with_float} in
-		"" | soft | hard)
+		"" | soft | hard | single | double)
 			# OK
 			;;
 		*)
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c	(Revision 200583)
+++ gcc/config/mips/mips.c	(Arbeitskopie)
@@ -16830,6 +16830,19 @@
 	target_flags &= ~MASK_FLOAT64;
     }
 
+  if (TARGET_HARD_FLOAT_ABI && TARGET_FLOAT64 && TARGET_MIPS5900)
+    {
+      /* FPU of r5900 only supports 32 bit. */
+      error ("unsupported combination: %s", "-march=r5900 -mfp64 -mhard-float");
+    }
+
+  if (TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT && TARGET_MIPS5900)
+    {
+      /* FPU of r5900 only supports 32 bit. */
+      error ("unsupported combination: %s",
+             "-march=r5900 -mdouble-float -mhard-float");
+    }
+
   /* End of code shared with GAS.  */
 
   /* If a -mlong* option was given, check that it matches the ABI,
@@ -17139,6 +17152,11 @@
      filling.  Registering the pass must be done at start up.  It's
      convenient to do it here.  */
   register_pass (&insert_pass_mips_machine_reorg2);
+
+  if (TARGET_MIPS5900)
+    {
+      REAL_MODE_FORMAT (SFmode) = &r5900_single_format;
+    }
 }
 
 /* Swap the register information for registers I and I + 1, which
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h	(Revision 200583)
+++ gcc/config/mips/mips.h	(Arbeitskopie)
@@ -859,7 +859,9 @@
 				 || TARGET_LOONGSON_2EF)
 
 /* ISA has LDC1 and SDC1.  */
-#define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1 && !TARGET_MIPS16)
+#define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1                             \
+                                  && !TARGET_MIPS16                     \
+				  && !TARGET_MIPS5900)			\
 
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */
@@ -989,7 +991,7 @@
 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
    instructions.  Both require TARGET_HARD_FLOAT, and trunc.w.d
    also requires TARGET_DOUBLE_FLOAT.  */
-#define ISA_HAS_TRUNC_W		(!ISA_MIPS1)
+#define ISA_HAS_TRUNC_W		(!ISA_MIPS1 || TARGET_MIPS5900)
 
 /* ISA includes the MIPS32r2 seb and seh instructions.  */
 #define ISA_HAS_SEB_SEH		((ISA_MIPS32R2		\