Hello!
I'm working with the program and I have a question. I have:
Next, I want to generate a verilog-file.
But in the generated verilog-file there is no description of the registers. Why? If I create ports, then they are in the generated verilog-file.
Last edit: Antipov Mikhail 2017-04-13
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Unfortunately, registers are not yet included in the generation. Earlier we actually had an experimental register feature in Verilog, but the end result was not satisfactory, so we decided to withdraw it until we could re-design it properly.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Hello!
I'm working with the program and I have a question. I have:
Next, I want to generate a verilog-file.
But in the generated verilog-file there is no description of the registers. Why? If I create ports, then they are in the generated verilog-file.
Last edit: Antipov Mikhail 2017-04-13
Hi,
Unfortunately, registers are not yet included in the generation. Earlier we actually had an experimental register feature in Verilog, but the end result was not satisfactory, so we decided to withdraw it until we could re-design it properly.