#77 Handling large signal lists

[Chris Stratton]

The structure window for selecting signals does not
deal well with having a huge number of singles in a
single module, such as arrises when simulating a
post-synthesis FPGA project where the design hierarchy
has been flattened during optimization.

Only a fraction of the signals are visible in the
structure browser. Signals not seen there can be added
with 'wave add' commands if one looks up the precise name.

Ideas:

- Figure out what is limiting the number of signals
that can be browsed within a single module

- Provide some sort of auto-complete type of search
function for signal names

- Provide a way to sort the signal names so that at
least what you are looking for will be in a consistent
place

(Problems experienced with .04-pre-20031121 precompiled
with associated iverilog version, both running on
windows, and launched from a cygwin shell)

[Chris Stratton]

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OOPS - my appologies, I've mis-stated the issue.

The problem is not actually with having a large number of
signals within a module, rather it is with having a large
number of sub modules within any given module, and not all
of these being displayed in the left half of the structure
window. If a submodule is displayed in the hierarchy and
selected, it's various signals are shown on the right as
expected.

(An FPGA synthesizer flattens the design and instantiates a
little module for every flip flop, buffer, etc required to
make it work. These are of little interest, but hiding
among them are the handfull of named modules that provide
archicture-specific implementations of word-width memories,
adders, multipliers, whose vector signals are the most
intersting internal signals still available to monitor
inside a compiled design)