Re: [Iverilog-devel] Syntax question, is !&x valid?

[Martin W. <ic...@ma...>]

On 30/03/2023 06:51, Niels Möller wrote:
> Hi,
> 
> I've noticed that icarus verilog doesn't like this piece of code:
> 
>    module foo(input [7:0] x, output y);
>       assign y = !&x;
>    endmodule
> 
> I'm running Icarus Verilog version 13.0 (devel)
> (s20141205-283-g437dc10), and it complains
> 
>    error: Operand of unary ! is not a primary expression.
> 
> Other tools, in particular yosys, seems to accept this syntax, and in
> general, I had expected that any stacking of unary operators is
> syntactically ok. Adding a pair of parentheses makes iverilog accept it,
> like
> 
>    module foo(input [7:0] x, output y);
>       assign y = !(&x);
>    endmodule
> 
> So my question is, what does the spec for verilog syntax say?

IEEE 1364-2005 appendix A says

expression ::=
     primary
   | unary_operator { attribute_instance } primary
   | expression binary_operator { attribute_instance } expression
   | conditional_expression

primary ::=
     number
   | hierarchical_identifier [ { [ expression ] } [ range_expression ] ]
   | concatenation
   | multiple_concatenation
   | function_call
   | system_function_call
   | ( mintypmax_expression )
   | string

so !&x is not valid syntax.

IEEE 1800-2017 adds more options, but does not change this.