[Iverilog-devel] Syntax question, is !&x valid?

[Niels M. <ni...@ly...>]

Hi, 

I've noticed that icarus verilog doesn't like this piece of code:

  module foo(input [7:0] x, output y);
     assign y = !&x;
  endmodule

I'm running Icarus Verilog version 13.0 (devel)
(s20141205-283-g437dc10), and it complains

  error: Operand of unary ! is not a primary expression.

Other tools, in particular yosys, seems to accept this syntax, and in
general, I had expected that any stacking of unary operators is
syntactically ok. Adding a pair of parentheses makes iverilog accept it,
like

  module foo(input [7:0] x, output y);
     assign y = !(&x);
  endmodule

So my question is, what does the spec for verilog syntax say?

Regards,
/Niels

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