Re: [Iverilog-devel] bit/part-select of function return value

[Cary R. <cy...@ya...>]

 I doubt this is super hard to implement, but I have no free time right now to look at what is involved. Please file a report on github. As Udi pointed out the correct syntax is wrapping the operand(s) in a concatenation.
Cary

    On Wednesday, March 10, 2021, 6:33:06 AM PST, Evan Lavelle <sa2...@cy...> wrote:  
 
 Xcelium 20.09, with -sysv:  No
VCS 2020.03, with -sverilog: Yes
Questa 2020.1:              Yes
Riviera-PRO 2020.04:        Yes

VCS allows this even without '-sverilog'. Weird. Unfortunately, I can't
personally use this, because the code has to run on Icarus as well.

On 10/03/2021 14:04, Udi Finkelstein wrote:
> Please take a look:
> https://github.com/verilator/verilator/issues/2619#issuecomment-781024235 <https://github.com/verilator/verilator/issues/2619#issuecomment-781024235>
> 
> Can you try putting it in a concatenation?
> 
> b= {f1(0)}[3:0]
> 
> Udi
> 
> 
> On Wed, Mar 10, 2021 at 3:04 PM Evan Lavelle <sa2...@cy...
> <mailto:sa212%2Bi...@cy...>> wrote:
> 
>    Icarus and VCS don't allow this, but Xcelium, Questa, and
>    Riviera-PRO do.
> 
>    The LRM does appear to agree with Icarus - the BNF only allows selects
>    of identifiers, and the explanatory text seems to agree ("Bit-selects
>    and part-selects of vector regs, integer variables, and time variables
>    shall be allowed").
> 
>    However, this is really pretty dumb: either a function returns an rvalue
>    that can be used in an expression, or it doesn't, in which case it's
>    something special and unusual. A function can return "Bit-selects and
>    part-selects of vector regs, etc", which indicates (to me, anyway) that
>    you should be able to apply a select to it.
> 
>    Might be worth going with Xcelium on this one?? OTOH, all the simulators
>    agree that you can't apply a select to a primary in general (8'ha5[3:0]
>    is illegal for all sims, for example), so maybe this is a step too far.
> 
>    Test code at https://www.edaplayground.com/x/9jLz
>    <https://www.edaplayground.com/x/9jLz>, and below:
> 
>    module test;
>      reg [7:0] a;
>      reg [3:0] b;
> 
>      initial begin
>        a = 8'ha5;
>        b = f1(0)[3:0];
>        $display("a is %b; b is %b", a, b);
>      end
> 
>      function [7:0] f1(input dummy);
>        f1 = a;
>      endfunction
>    endmodule
> 
> 
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