Re: [Iverilog-devel] -Wtimescale issue

[Cary R. <cy...@ya...>]

 Hi Even,
The compiler has no idea the inherited time scale is intended so warns about that. I believe you can turn the warning off. The commercial tools I have used do the same except Icarus is smart enough to not warn about modules that do not use any delays. This is not the case for the commercial tool I use the most. It warns for every module.

The intent of the warning is to inform the user that the timescale being used in the module is not defined in the file so the timescale needs to be verified. This gets very confusing when some, but not all files define a timescale. For your case where you know what you are doing and it has been thought out I would just disable the warning.
Cary

    On Thursday, January 28, 2021, 9:12:48 AM PST, Evan Lavelle <sa2...@cy...> wrote:  
 
 In an environment where you have one testbench file and multiple RTL
files, it is common to have a single timescale in the TB file, and no
timescale directives in the RTL code.

However, if you compile this as 'iverilog -Wtimescale tb.v rtl1.v ..
rtln.v', you get a timescale warning ('warning:timescale for rtl1.v
inherited from another file').

This inheritance is exactly what you want in this case, and is valid (of
course, if the timescale is not in the first file compiled, there's an
issue).

I can see that the warning would make sense if Icarus compiled each file
independently and linked the results, but it doesn't. Thoughts?


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