[Iverilog-devel] Specify block support?

[Evan L. <sa2...@cy...>]

What's the status of specify block support? Are timing checks meant to work?

https://www.edaplayground.com/x/ex57
<https://www.edaplayground.com/x/ex57> is a simple hard-wired test of
$setuphold. This drives the data input of a F/F with a valid setup, but
with a hold failure. The test passes if the simulator reports a hold
violation, and the testbench reports  "**FAIL** setup or hold failure: q
is x". Questa, for example, correctly reports:

# ** Error: $hold( posedge clock:15 ns, data:16 ns, 2 ns );
# Time: 16 ns Iteration: 1 Process: /top/dff/#Setuphold# File:
testbench.sv Line: 47
# **FAIL** setup or hold failure: q is x

This test passes on Veriwell, Riviera PRO, VCS, Xcelium, Questa, and
ModelSim. It partially passes on GPL Cver - Cver reports a hold failure,
but the notifier mechanism appears to be broken, and the testbench
reports a pass, instead of a fail. Icarus 11.0 appears to ignore the
specify block and the testbench (incorrectly) reports that the test passed.

Thanks.