Re: [Iverilog-devel] Small stuff

[Martin W. <ic...@ma...>]

On 03/10/2020 08:08, Evan Lavelle wrote:
> On 01/10/2020 14:47, Martin Whitaker wrote:
> 
>> Can you give an example of this.
> 
> Ok, worked it out: if the task is declared with brackets around the
> formals, but there are no formals, then a warning is raised. If the task
> is declared without brackets, then no warning is raised.
> 
> I guess the square brackets around 'task_port_list' below weren't noticed?
> 
> -E
> 
> task_declaration ::= (From A.2.7)
>      task [ automatic ] task_identifier ;
>        { task_item_declaration }
>        statement_or_null
>        endtask
>    | task [ automatic ] task_identifier ( [ task_port_list ] ) ;
>        { block_item_declaration }
>        statement_or_null
>      endtask

That warning was added in this commit:

commit 46350da5f0f3c623cb9fe05003d7e2b8506d14a7
Author: Cary R <cy...@ya...>
Date:   Fri Apr 3 18:55:48 2009 -0700

     Add support for empty task port lists with a warning.

     The standard does not allow this, but it appears that other
     simulators do. This patch adds the functionality, but prints
     a warning message for the invalid task definition.

so it seems your guess is correct, unless Cary was looking at the 2001 
standard, which doesn't make task_port_list optional.

I've fixed this in both the master and v11 branches. The warning is now 
only issued if you select a Verilog language generation < 2005.