Re: [Iverilog-devel] Is it illegal to use an (enum) as a function input?

[Stephen W. <st...@ic...>]

Icarus Verilog does support enum arguments to functions.
See pull371b.v in the ivtest test suite.

On Sat, Sep 19, 2020 at 11:18 PM Cary R. via Iverilog-devel
<ive...@li...> wrote:
>
> I believe Icarus does not currently support using enums as function arguments.
>
> Cary
> On Saturday, September 19, 2020, 8:55:30 AM PDT, Kevin Simonson <kvn...@ho...> wrote:
>
>
> I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I was waiting for input on that I decided to rewrite a version of my Verilog code to use an (enum) instead of a (boolean). Much to my amazement, it appears that I can't use an (enum) as an input to a function either! I wrote the following code:
>
> module useBin ();
>
> typedef enum { ADD, MULTIPLY } binOp;
>
> function integer execOp;
>     input integer left;
>     input integer right;
>     input   binOp op;
>   begin
>     execOp = op == ADD ? left + right : left * right;
>   end
> endfunction
>
> endmodule
>
> When I ran Icarus to simulate it I got:
>
> D:\Hf\Verilog\Unpacked\Common>ive useBin
> \Icarus\bin\iverilog -g2009 -o useBin.out useBin.sv
> useBin.sv:8: syntax error
> useBin.sv:5: error: Syntax error defining function.
>
> D:\Hf\Verilog\Unpacked\Common>
>
> I can kind of understand why a (boolean) might cause a problem when used as a function input, but why in the world would it be illegal to use an (enum) like my (binOp) as a function input?
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