From: <bo...@el...> - 2020-06-17 13:40:56
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Cary R. via Iverilog-devel writes: > It should be possible and I was hoping to look at what was needed to implement > this over the weekend. Hello Cary, the question was half an offer that I could look into it. However my incentive diminished as the problem was with an 2010 Spartan 6 design where I have to use ISE for implementation and ISE does not cope with arrays in the module headers. In the meantime I rewrote the code to use vectors and I no longer need the array functionality with the more recent verilog language versions. Bye -- Uwe Bonnes bo...@el... Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 1623569 ------- Fax. 06151 1623305 --------- |