Re: [Iverilog-devel] Verilog execution of always block as multiple events

[<by...@nc...>]

BTW, one difference between Icarus and VCS/Questa that I've noticed is
that events on packed arrays on those simulators are only triggered
for writes to a given array index's bitvector, not the whole packed
array.

I've had to ifdef code for Icarus where:
wire [7:0][7:0] mybits;
were
logic [7:0] mybits [7:0];

in order to function correctly. The logic thing is a separate issue
elsewhere as VCS and Questa can handle non-constant array indices in
almost all cases and Icarus can only in a subset of them.

So for the above, if I have access to a packed array across multiple
instances in a generate, there are times where Icarus goes into an
infinite retrigger condition whereas VCS/Questa gracefully complete
properly. Synopsys DC, VCLint, etc. can handle that packed construct
across multiple generate iterations fine as well.

-Tony