Re: [Iverilog-devel] Verilog execution of always block as multiple events

[Evan L. <sa2...@cy...>]

On 17/05/2020 07:11, Julian Thomas Parkin wrote:
> Thanks for the explanations everyone, very helpful.
> 
> Would I be correct in summarizing this as, the standard doesn't
> strictly require an always block to run uninterrupted until it
> suspends on its own, but there's a lot of inertia behind the
> assumption that it does (an "unwritten rule" as Steve calls it) to
> the point that it's a safe assumption to make when writing Verilog.

Basically, yes, but the unwritten rule is occasionally broken. The
scheduler is event-driven, not pre-emptive; it shouldn't arbitrarily
decide when to transfer control between different processes. But, OTOH,
the LRM does *not* specify atomic execution of code between scheduling
points, and explicitly says in 11.4.1(a) that "Execution of statements
in a particular begin-end block can be suspended in favor of other
processes in the model".

Steven Sharp covered this in comp.lang.verilog at

https://groups.google.com/forum/?hl=en#!topic/comp.lang.verilog/2X9f9ds9XnE

as follows (in other words, this is as Gospel as it gets for Verilog):

"There is the rigamarole about allowing a begin-end to suspend in favor
of executing another process, and then resume later.  If taken to
extremes, this would make the language very hard to use, since many
common practices would become nondeterministic.  This seems to have
been stated partly to allow for simulator optimizations involving
inlining of one process into another.  For example, when an always
block updates a variable, a simulator might immediately update a net
that is assigned from that variable.  This can be viewed as suspending
the always block, executing the continuous assignment, and then
resuming the always block.  But no simulator is going to arbitrarily
suspend one process to execute another, unless there is at least some
kind of event-driven connection between them".

I'm sure this is covered elsewhere in c.l.v, but it's next to useless
now, since Google removed the advanced search.

But not all simulators play ball. See:

https://groups.google.com/forum/#!searchin/comp.lang.verilog/%22STEVEN$20SHARP%22$20scheduler|sort:date/comp.lang.verilog/tK-MpHdfVCE/uGAgIp4BpBIJ

Look up my comment for:

x = add(x, 1);

I found one simulator where this wasn't atomic. This was a long time ago
(2008), and I don't have notes, so I don't know which sim it was.