Re: [Iverilog-devel] Verilog execution of always block as multiple events

[Douglas S. <dc...@tr...>]

Julian,

In the case you mention, the always block will finish the update due to 
a changing, and then activate again because b changed. If we say that a 
changes from a0 to a1, and b changes from b0 to b1, then c will change 
from a0 & b0 to a1 & b0, and then to a1 & b1.

And since it could have updated b before the assignment to temp, it 
could have gone from a0 & b0 directly to a1 & b1. Since you are not 
specifying any delays here, I assume that a and b are changing "at the 
same time" (but not the same simulator cycle), so of course b could be 
the one to trigger the always block, giving a different intermediate 
state for c.

I remember someone saying "Time is natures way of ensuring that 
everything doesn't happen all at once." In verilog, time is the only way 
to ensure sequencing of signals: you can't assume the order of signals 
changing at the same time, and verilog will remain at that time 
(re-triggering any always blocks, gates, assign statements ...) until no 
more events are scheduled for that time.

Doug Sojourner

On 05/16/20 13:55, Julian Thomas Parkin wrote:

This isn't an issue with iverilog, but I have a question about the
execution semantics of Verilog. There isn't much information online
and a lot of it points to this mailing list
(e.g. https://sourceforge.net/p/iverilog/mailman/message/36358575/)
so I'm hoping it's alright if I ask here.

In 1364-2005, section 11.4.2 includes the following sentence (which
is also present in SystemVerilog): "Another source of nondeterminism
is that statements without time-control constructs in behavioral
blocks do not have to be executed as one event."

As an example, it presents the following:

   assign p = q;
   initial begin
       q = 1;
       #1 q = 0;
       $display(p);
   end

The simulator is allowed to process the "q = 0" assignment, then
suspend execution in favour of updating p, and then display p as 0.

Does this also apply to the typical style of always process used
to express combinatorial circuits ?

For example, if someone were to implement an and gate using a
temporary variable:

   always @(a or b) begin
       temp = a & b;
       c = temp;
   end

Say a and b both have pending update events. Could the simulator
update a, see that the always has been activated, execute
"temp = a | b;", then suspend execution to update b ? At which
point the always block is not sensitive to changes because it is
still being executed, so it ends up missing the second update even
though b is in the sensitivity list.

Is this valid behavior according to the standard ? Or does
"statements without time-control constructs" apply to the
"begin end" block as a whole and prevent it from being executed as
multiple events because it does have a time-control ? If this is
valid, do iverilog or other simulators ever behave in this manner ?


Thanks,

-Julian


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