Re: [Iverilog-devel] Verilog execution of always block as multiple events

[Cary R. <cy...@ya...>]

 
In a multi threaded simulator this is certainly possible unless it has created some kind of dependency graph. Most/maybe all single threaded simulators and icarus specifically will execute the currently running process until it reaches some kind of time statement (the @ in this code) before switching to the next process. The order of the processes running is not deterministic, though most simulators use a FIFO queue so there is some known determinism for a specific simulator.
It would require a well controlled seed for repeatability, but I always thought pulling a random element from the queue would over many regressions find most timing races that people code, but never get bitten by since their simulator has at least some determinism.
Cary
    On Saturday, May 16, 2020, 3:05:26 PM PDT, Julian Thomas Parkin <jtp...@uw...> wrote:  
 
 This isn't an issue with iverilog, but I have a question about the
execution semantics of Verilog. There isn't much information online
and a lot of it points to this mailing list
(e.g. https://sourceforge.net/p/iverilog/mailman/message/36358575/)
so I'm hoping it's alright if I ask here.

In 1364-2005, section 11.4.2 includes the following sentence (which
is also present in SystemVerilog): "Another source of nondeterminism
is that statements without time-control constructs in behavioral
blocks do not have to be executed as one event."

As an example, it presents the following:

  assign p = q;
  initial begin
      q = 1;
      #1 q = 0;
      $display(p);
  end

The simulator is allowed to process the "q = 0" assignment, then
suspend execution in favour of updating p, and then display p as 0.

Does this also apply to the typical style of always process used
to express combinatorial circuits ?

For example, if someone were to implement an and gate using a
temporary variable:

  always @(a or b) begin
      temp = a & b;
      c = temp;
  end

Say a and b both have pending update events. Could the simulator
update a, see that the always has been activated, execute
"temp = a | b;", then suspend execution to update b ? At which
point the always block is not sensitive to changes because it is
still being executed, so it ends up missing the second update even
though b is in the sensitivity list.

Is this valid behavior according to the standard ? Or does
"statements without time-control constructs" apply to the
"begin end" block as a whole and prevent it from being executed as
multiple events because it does have a time-control ? If this is
valid, do iverilog or other simulators ever behave in this manner ?


Thanks,

-Julian


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