Re: [Iverilog-devel] Support for experimental logic states

[Evan L. <sa2...@cy...>]

> Could you elaborate on how it would be trivial in VHDL? Do you mean this 
> type already exists or can be easily modified, e.g., something similar 
> to std_ulogic? Or are you saying it is trivial to create, e.g., 
> importing a package that defines this type with the appropriate 
> resolution table?

I would just create the type (multi-value logic types are enumerated, 
and you just add your own). This is exactly what VHDL is for - not fast, 
but very flexible. The vendors all had their own incompatible MVL types 
in the early 80's, before std_logic_1164 came along, with a standardised 
9-value type (std_ulogic). I would just copy std_logic_1164 (lots of 
sources online) for your own 4-(or more-)value MVL, add a resolution 
function and some overloads, and you're done. The vendors will 
accelerate their own implementations of std_[u]logic, and you won't get 
that, of course.

> 
> My preference for Verilog comes from the availability of a mature 
> open-source simulator. The only VHDL simulator I have seen/used is GHDL 
> but I'm not sure development is active (hasn't been updated since 2010). 

You must be on the wrong website! GHDL is very active. I only use the 
commercial sims, though, so don't know anything about it.

> My goal is to maximize performance. I noticed that the Mentor Graphics 
> tool vsim processes 'x' signals in Verilog faster than other signals. I 
> wanted to study this effect and potentially use it.

I don't know about performance - any MVL is going to be relatively slow. 
Having said that, GHDL is probably fast (it has LLVM and GCC back-ends), 
and if it accelerates std_ulogic, maybe you could hack into that.

I don't think ModelSim's vsim is known for speed. They started out with 
VHDL, and I always got the impression that the later Verilog back-end 
was the same as the VHDL one, but it's just an impression.