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Re: [Iverilog-devel] Support for experimental logic states
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From: Daniel L. <dan...@nc...> - 2020-02-12 15:48:12
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Thanks for the response, Evan. Could you elaborate on how it would be trivial in VHDL? Do you mean this type already exists or can be easily modified, e.g., something similar to std_ulogic? Or are you saying it is trivial to create, e.g., importing a package that defines this type with the appropriate resolution table? My preference for Verilog comes from the availability of a mature open-source simulator. The only VHDL simulator I have seen/used is GHDL but I'm not sure development is active (hasn't been updated since 2010). My goal is to maximize performance. I noticed that the Mentor Graphics tool vsim processes 'x' signals in Verilog faster than other signals. I wanted to study this effect and potentially use it. Regarding the delay in receiving my post, I am a new member so it may have taken time for me to get confirmed. Daniel -- Daniel Limbrick, Ph.D. Associate Professor Electrical and Computer Engineering Department North Carolina A&T State University 523 McNair Hall Greensboro, NC 27411 Office: 336-285-3310 E-mail: dan...@nc...<mailto:dan...@nc...> Web page: http://daniellimbrick.com On Wed, Feb 12, 2020 at 4:54 AM Evan Lavelle <sa2...@cy...<mailto:sa212%2Bi...@cy...>> wrote: Wouldn't this just be trivial with VHDL? Is there any particular reason to use Verilog? Looks like your message took 6 days to get through to the list. On 06/02/2020 17:44, Daniel Limbrick wrote: > I am a researcher at North Carolina A&T State University working on > simulating faults in digital circuits. I am using your simulator Icarus > Verilog and I wanted to experiment with adding new states of logic > (beyond 0,1,x and z). I wanted to copy the specification for "x" and > create a version that keeps track of the polarity of "x". > > Do you have any documentation or notes that might help me understand how > to add this functionality? Also, is there an API for Icarus extensions? > Any help would be greatly appreciated. Thanks. > > Daniel > > -- > Daniel Limbrick, Ph.D. > Associate Professor > Electrical and Computer Engineering Department > North Carolina A&T State University > 523 McNair Hall > Greensboro, NC 27411 > Office: 336-285-3310 > E-mail: dan...@nc...<mailto:dan...@nc...> <mailto:dan...@nc...<mailto:dan...@nc...>> > Web page: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&data=02%7C01%7Cdblimbri%40ncat.edu%7Cc648539418484bfa34f608d7afa397dc%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637170990069986489&sdata=PzGsR2%2BqXwULH%2FAORuM0DdcecbtfxmxsnTom3m%2Bz%2Fcg%3D&reserved=0 > ------- NOTICE: This e-mail correspondence is subject to Public Records > Law and may be disclosed to third parties. -------- > > > _______________________________________________ > Iverilog-devel mailing list > Ive...@li...<mailto:Ive...@li...> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&data=02%7C01%7Cdblimbri%40ncat.edu%7Cc648539418484bfa34f608d7afa397dc%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637170990069986489&sdata=4YDqU%2B9x%2BT2qUVS3Sz44dOSTG1gtyOQcj5ODOpIx%2FWM%3D&reserved=0 > _______________________________________________ Iverilog-devel mailing list Ive...@li...<mailto:Ive...@li...> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&data=02%7C01%7Cdblimbri%40ncat.edu%7Cc648539418484bfa34f608d7afa397dc%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637170990069986489&sdata=4YDqU%2B9x%2BT2qUVS3Sz44dOSTG1gtyOQcj5ODOpIx%2FWM%3D&reserved=0 ------- NOTICE: This e-mail correspondence is subject to Public Records Law and may be disclosed to third parties. -------- |
