[Iverilog-devel] Support for experimental logic states

[Daniel L. <dan...@nc...>]

I am a researcher at North Carolina A&T State University working on simulating faults in digital circuits. I am using your simulator Icarus Verilog and I wanted to experiment with adding new states of logic (beyond 0,1,x and z). I wanted to copy the specification for "x" and create a version that keeps track of the polarity of "x".

Do you have any documentation or notes that might help me understand how to add this functionality? Also, is there an API for Icarus extensions? Any help would be greatly appreciated. Thanks.

Daniel

--
Daniel Limbrick, Ph.D.
Associate Professor
Electrical and Computer Engineering Department
North Carolina A&T State University
523 McNair Hall
Greensboro, NC 27411
Office: 336-285-3310
E-mail: dan...@nc...<mailto:dan...@nc...>
Web page: http://daniellimbrick.com
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