Re: [Iverilog-devel] Issues using system verilog model

[Douglas S. <dc...@tr...>]

Martin,

Thank you for your reply. I'll try to create some simple example of the 
fails I've seen.

Regards,
Doug

On 01/20/20 14:34, Martin Whitaker wrote:
> Sorry you haven't had a reply sooner - your message appears to have 
> got stuck on the SourceForge server for two weeks.
>
> enum types are mostly supported, so if you find problems, please open 
> bug reports, giving a simple example, and mentioning what version of 
> iverilog you are using. These days, most bugs are reported as issues 
> on GitHub.
>
> I don't think there's any way to work around unsupported behaviour 
> like you suggest.
>
> Douglas Sojourner wrote:
>> I realize that iverilog does not claim to fully support system 
>> verilog, so this is a request for help, not a complaint.
>>
>> There are a number of enum types delcared in the files for this 
>> model, and they are causing problems in several ways:
>> 1) In a package, a number of parameters are delcared as enum types. 
>> The compile fails with a "syntax error" message pointing to the 
>> appropriate line.
>> 2) Some functions have parameters or return values that are enum 
>> types. In this case iverilog silently hangs while elaborating.
>>
>> In all cases, changing the type to int works. Is there a 
>> straightforward way to cause iverilog to treat enums as ints in 
>> contexts where it does not explicitly recognize them?
>>
>> Thanks for your help,
>>
>> Doug Sojourner
>>
>>
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>
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