[Iverilog-devel] Issues using system verilog model

[Douglas S. <dc...@tr...>]

I realize that iverilog does not claim to fully support system verilog, 
so this is a request for help, not a complaint.

There are a number of enum types delcared in the files for this model, 
and they are causing problems in several ways:
1) In a package, a number of parameters are delcared as enum types. The 
compile fails with a "syntax error" message pointing to the appropriate 
line.
2) Some functions have parameters or return values that are enum types. 
In this case iverilog silently hangs while elaborating.

In all cases, changing the type to int works. Is there a straightforward 
way to cause iverilog to treat enums as ints in contexts where it does 
not explicitly recognize them?

Thanks for your help,

Doug Sojourner