Re: [Iverilog-devel] run time crash with the newest compiled version from git

[Martin W. <ic...@ma...>]

Yes, this is https://sourceforge.net/p/iverilog/bugs/916/.

If you try the same thing with $monitor, you get the following message:

SORRY: test.v:6: currently only simple signals or constant expressions may 
be passed to $monitor.
NOTE: You can work around this by assigning the desired expression to an
       intermediate net (using a continuous assignment) and passing that net
       to $monitor.

and you can use the same workaround.

Ideally we'd output a similar message in your case, but we don't know what 
a user-defined system function is going to do with its arguments.

fuyong wrote:
> um,, the same code actually can work with commercial simulator. Any
> suggestion on how to change the coding?
> 
> On Mon, Dec 23, 2019 at 4:05 AM Martin Whitaker <
> ic...@ma...> wrote:
> 
>> You are getting a vpiHandle to a temporary value (the evaluation of the
>> expression {src1,dst2}) in the call to $put_flag and using it in your
>> EndOfSimTime callback. That can't work - the temporary value only exists
>> for the lifetime of the call to $put_flag.
>>
>> Yong Fu wrote:
>>> Hi,
>>>
>>> Have put a test case in git:
>>>
>>> https://github.com/tangeraise/iv_debug
>>>
>>> Thanks,
>>>
>>>> On Dec 21, 2019, at 1:15 PM, Martin Whitaker <
>> ic...@ma...> wrote:
>>>>
>>>> fuyong wrote:
>>>>> Hi,
>>>>> We are compiling the new version from git to check mainly the new VPI
>>>>> feature of EndOfSimTime. And we have met the runtime error:
>>>>> vvp -M . -m vpi1 a.out
>>>>> vvp: vthread.cc:138: const vvp_vector4_t& vthread:s:peek_vec4(unsigned
>>>>> int): Assertion `depth < size' failed.
>>>>> Any chance to tell what is wrong?
>>>>
>>>> Not without a test case that allows us to reproduce the error.
>>>>
>>>>
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