[Iverilog-devel] Scope visibility within classes

[Martin W. <ic...@ma...>]

Consider this example:

   module test;

     integer i;

     class myclass;
       integer j;
       function void init();
         j = i;
       endfunction
     endclass

   endmodule

This example example compiles without error on EDA playground. But iverilog 
outputs the following error message:

   test.v:8: error: Unable to bind wire/reg/memory `i' in `myclass.init'

In elab_scope.cc there is this comment:

   // Class scopes have no parent scope, because references are
   // not allowed to escape a class method. But they are allowed
   // to reference the compilation unit scope.

but I can find no justification for this in the IEEE standard. So where did 
this come from?