Re: [Iverilog-devel] any plan for implement cbAtStartOfSimTime?

[Stephen W. <st...@ic...>]

I think that you already have what you need. cbAtStartOfSimTime is
already implemented, and cbReadOnlySync can then be scheduled to be
called at the end of the simulation time.

On Wed, Nov 20, 2019 at 12:00 AM fuyong <fuy...@gm...> wrote:
>
> Hi,
>
> At first, I think cbAtEndOfSimTime and cbAtBeginOfSimTime could be used similarly, as the data at the end of one Sim Time is the beginning of the next Sim Time. We have a project , to partition a big design into several pieces. Each piece will run in one simulator. VPI put/get_value are used to communicate in between the several iverilog processes.  So the question is, if we use AtStartofSimTime, the data passed from partition #1 to partition #2 will be the data of the previous simulation time slot, then the waveform will show like one cycle delayed. to pass data use AtEndOfSimTime will not have this issue in commercial simulator.
>
> Any plan to implement AtStarOfSimTime?
>
>
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