Re: [Iverilog-devel] Assume a DUT is split into two partitions and each partition run in a iVerilog program...

[Stephen W. <st...@ic...>]

This sort of situation is addressed with the simbus project. The exact
intent of simbus is to detach the test bench and dut into separate
processes, and even different languages.

On Tue, Nov 5, 2019 at 2:33 PM fuyong <fuy...@gm...> wrote:
>
> A brainstorming for parallel simulation.
>
> Assuming the following design:
>
> module TB;
>      ...
>     always #5 clk = ~clk;   // generate original clock
>      // a gated clock that will be used in subinstance M1
>     assign gated_clock = clk & a_net_generated_in_this_module;
>
>     always @(posedge clk)   Q <= something;  // non blocking, output to M1
>
>      M1 M1_inst (gated_clk, Q, ...);
> endmodule
> module M(clk, din, dout...);
>
> We want TB run in one iverilog program, and M1 run in another. The real TB and M1 could be large, doing so might give some perf improvement. Interface between TB and M1 is not too complicated, so manual partition is OK.
>
> Question is, what is the good time region at a simulation time slot should gated_clock and Q send from tb to M1? I assume Q at ArEndOfSimTime (postponed) , and gated_clock at NBASynch(pre-NBA) might be the most safe one. But this means at one time slot two VPI calls ( or even more consider the iteratinos?) should be used so runtiem performance impacted. And another thing is iVerilog does not have pre-NBA implemented in the current version.
>
> Or any other suggestions?
>
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel



-- 
Steve Williams                "The woods are lovely, dark and deep.
st...@ic...              But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."