Re: [Iverilog-devel] Priority case and default case items.

[Bryan M. <bmu...@gm...>]

This paper has a lot of explanation about priority (and unique):

http://www.sutherland-hdl.com/papers/2005-SNUG-paper_SystemVerilog_unique_and_priority.pdf

My quick summary is that they are directives meant mostly for synthesis
tools.  If someone provides a default case in their priority case, yes,
they are making the priority statement redundant in the simulation, but it
might still be a very important directive for synthesis.  So don't nag them
about it with a warning 🙂

Bryan


On Wed, Oct 9, 2019, 10:39 AM Stephen Williams <st...@ic...> wrote:

> Here's a question. There is this:
>
> priority case (foo)
>  1: stmt1;
>  2: stmt2;
>  default: stmt_default;
> endcase
>
> The priority case "shall issue a violation report if no case_item matches."
>
> The default: statement makes it so that every possible value of foo
> has a case item, if the "default" case is considered a case item, and
> by the BNF, it is indeed a case_item. But the "default:" makes the
> "priority" moot. So should this print a violation message or not?
>
> (I'm thinking, it should not, but a compile time warning may make
> sense. But I can see logic for the other course too.)
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> st...@ic...              But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
>
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