[Iverilog-devel] Help: Seems like recursive function is not supported?

[fuyong <fuy...@gm...>]

Hi,

We have download a design from Github. This design can run correctly in
VCS. But iVeriog compile hang.

https://github.com/unixb0y/SystemVerilogSHA256

Guess it is the following function (recursive function as it call itself)
cause the issue:

    function automatic [31:0] W;
        input [6:0] x;
        input [6:0] y;
        if(^x === 1'bX) W = 32'h777;
        else W = (x<16) ? padded[((PADDED_SIZE-1-y*512)-x*32) -: 32] :
rho1(W(x-2, y)) + W(x-7, y) + rho0(W(x-15, y)) + W(x-16, y);
    endfunction

Any suggestions on how to change the code for workaround? Or enhancement in
iVerilog :-) ?

Thanks,
Yong