[Iverilog-devel] SystemVerilog timeunit

[Galen S. <ga...@se...>]

Hi,

Is SystemVerilog timeunit supported?  I see that there are
some timeunit tests in regress-sv.list.

I have timeunit inside a package which I am importing into
a module, but I get a related warning.  This is the first
time I have attempted to use timeunit, so there's a good
chance I'm doing something wrong.

package my_globals;
   timeunit 1ns/1ns;
...
endpackage

module flags
  import my_globals::*;
  #(parameter I_WIDTH = 18)
   (
    input 		clock,
    input 		reset,
    input fsm_out_t     fsm_out,
    input [I_WIDTH-1:0] instr,
    input 		carry,
    input 		zero,
    output logic 	carry_flag,
    output logic 	ie_flag,
    output logic 	zero_flag
    );
...
endmodule

[galens@toto]$ iverilog -Wall -g2012 my_globals.sv flags.sv -o /dev/null
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- module flags declared here: flags.sv:3


Also on the subject of SystemVerilog, support for case...inside would
really be useful.  Of course from my perspective, any support for more of
the synthesizable constructs would be welcome.


thanks,
galen
-- 
Galen Seitz
ga...@se...