Re: [Iverilog-devel] SystemVerilog Support

[Cary R. <cy...@ya...>]

 Surprisingly, Steve is the odd man out being the only one who primarily works as a programmer. Both Martin and I are are primarily chip designers. There are multiple ways to contribute. You could start just documenting what is implemented and get us good release notes for V10 and what has been added to development which will eventually become V11. If you want to help with the code then what is your experience in C++? There are many other ways to help if we know your background and what interests you.

Cary

    On Monday, August 26, 2019, 12:02:28 AM PDT, Hagen SANKOWSKI <hs...@no...> wrote:  
 
 Hello Martin.

Quoting Martin Whitaker <ic...@ma...>:

>> What's about the support for SystemVerilog?
>> Are there some planes to support SystemVerilog?
>
> There is already support for some SystemVerilog features.  
> Unfortunately there's no definitive list of what is or isn't  
> supported, but you can look in the test suite to get an idea:
>
>  https://github.com/steveicarus/ivtest/blob/master/regress-sv.list
>
> Cary intends to complete the support for always_comb et al., but I'm  
> not aware of any plans to add support for more features.


Thanks to point me to the test suite..

Indeed it is a good resource for investigation. I like to support the  
effort to widen the list of supported SystemVerilog features up to  
IEEE 1800-2017 (which is IMHO a good stable language feature set).  
Unfortunately I am VLSI chip designer, not a programmer..

Let's see, what I can do so far.

Regards,
Hagen Sankowski

-- 
"They who can give up essential liberty to obtain a little temporary
safety, deserve neither liberty nor safety." Benjamin Franklin (1775)



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