Re: [Iverilog-devel] SystemVerilog Support

[Hagen S. <hs...@no...>]

Hello Martin.

Quoting Martin Whitaker <ic...@ma...>:

>> What's about the support for SystemVerilog?
>> Are there some planes to support SystemVerilog?
>
> There is already support for some SystemVerilog features.  
> Unfortunately there's no definitive list of what is or isn't  
> supported, but you can look in the test suite to get an idea:
>
>   https://github.com/steveicarus/ivtest/blob/master/regress-sv.list
>
> Cary intends to complete the support for always_comb et al., but I'm  
> not aware of any plans to add support for more features.


Thanks to point me to the test suite..

Indeed it is a good resource for investigation. I like to support the  
effort to widen the list of supported SystemVerilog features up to  
IEEE 1800-2017 (which is IMHO a good stable language feature set).  
Unfortunately I am VLSI chip designer, not a programmer..

Let's see, what I can do so far.

Regards,
Hagen Sankowski

-- 
"They who can give up essential liberty to obtain a little temporary
safety, deserve neither liberty nor safety." Benjamin Franklin (1775)