Re: [Iverilog-devel] running iverilog and vvp from the build tree (no make install)

[Evan L. <sa2...@cy...>]

On 09/08/2019 01:28, Galen Seitz wrote:
> Hello again,
> 
> In order to track down the commit that caused the behavior change 
> between 0.9 and 0.10 that is being discussed in another thread,

I wouldn't bother. If Martin's right (and I'm sure he is) then this is a 
'feature' in the Lattice model, and whether or not Q initialises 
correctly is just a roll of the dice (but probably deterministic for a 
given simulator). You may be able to find a switch on one of the other 
simulators to randomise the initialisation order, which would be 
interesting - you should find that Q resets on some runs but not on 
others (Steve wanted to do this for Icarus, but I don't think it ever 
happened).

This is exactly what SV's 'always_comb' is meant to fix. This was a very 
late attempt to rationalise simulation start-up in Verilog (to, 
curiously, exactly what VHDL had done since day #1).