Re: [Iverilog-devel] possible regression in 0.10 when simulating Lattice FF

[Evan L. <sa2...@cy...>]

On 08/08/2019 18:09, Galen Seitz wrote:

> My testbench generates a reset signal that is 2 clocks long.  The D 
> input is tied to 0, and the enable is tied to 1.  Notifier is an 
> internal signal of FD1P3DX and is X, but that doesn't seem to impact the 
> simulation.

You really need to write a testbench that instantiates a single 
UDFDL5E_UDP_X, and then drives D, CK, CE, CLR, and notifier with 
whatever they're doing in your real design for those 2 cycles. That 
would be sufficient to show whether or not the UDP handling has broken. 
My suspicion is that 'notifier' is changing from something to X, which 
would result in what you're seeing. That wouldn't really help, though, 
since it would point to a (timing) error in whatever is instantiating 
the UDP in your design.