Re: [Iverilog-devel] possible regression in 0.10 when simulating Lattice FF

[Evan L. <sa2...@cy...>]

Is this:

https://github.com/flexSD/flexSD/blob/master/XP2%20Verilog%20Primitives/UDFDL5E_UDP_X.v

the UDP that's failing?

If so, how are you driving it? What are the D, CK, CE, CLR, and notifier 
inputs doing at or soon after time 0?