Re: [Iverilog-devel] VHDL compile errors

[Maciej S. <mac...@ce...>]

Hi David,

VHDL support in Icarus is very limited and currently is done by
compiling VHDL files to SystemVerilog. We have learnt that even though a
significant part of the VHDL standard could be covered, most likely we
will not be able to implement a complete VHDL simulator this way. Due to
that, the concept has been abandoned and IIRC nobody works on VHDL
frontend in Icarus right now.

It would be much better to join a dedicated (System)Verilog simulator
(e.g. Icarus) and a dedicated VHDL simulator (e.g. ghdl) and exchange
data between them, but I think nobody volunteered to do that either.

Regards,
Orson

On 07/02/2018 08:34 PM, David Fong wrote:
> Hi,
> 
> I'm trying to compile a VHDL package file and I'm getting these errors
> 
> ../commonlib/types_common.vhd:63: syntax error
> ../commonlib/types_common.vhd:63: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:64: syntax error
> ../commonlib/types_common.vhd:64: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:67: syntax error
> ../commonlib/types_common.vhd:67: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:67: syntax error
> ../commonlib/types_common.vhd:67: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:68: syntax error
> ../commonlib/types_common.vhd:68: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:69: syntax error
> ../commonlib/types_common.vhd:69: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:69: syntax error
> ../commonlib/types_common.vhd:69: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:70: syntax error
> ../commonlib/types_common.vhd:70: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:71: syntax error
> ../commonlib/types_common.vhd:71: error: Syntax error in package declarative item.
> ../commonlib/types_common.vhd:71: syntax error
> ../commonlib/types_common.vhd:71: error: Syntax error in package declarative item.
> 
> 63 function "-"
> 64 (i : integer; d : std_logic_vector)
> 65 return std_logic_vector;
> 66
>  67 function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
> 68 function "-" (a, b : std_logic_vector) return std_logic_vector;
> 69 function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
> 70 function "+" (a, b : std_logic_vector) return std_logic_vector;
> 71 function "+" (d : std_logic_vector; i : std_logic) return std_logic_vector;
> 
> Looks like iverilog cannot handle overloaded functions or the string named function "-"  or "+"
> 
> David
> 
> 
> 
> 
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