[Iverilog-devel] VHDL compilation error due to "length" attribute, "line" type and "unary" and "loop"

[David F. <da...@ch...>]

Hi,

I got some more VHDL compilation errors when I comment out lines in types_util.vhd

Please confirm if these are not able to compile with current iverilog

Thanks,

David

./types_util.vhd:124: syntax error

./types_util.vhd:152: error: Can't find type name `line'
./types_util.vhd:157: sorry: Unary expression +- not supported.
./types_util.vhd:162: syntax error
./types_util.vhd:162: error: Syntax error in sequential statement.
./types_util.vhd:157: sorry: Loop statements are not supported.

123   function tost(v:std_logic_vector) return string is
124     constant vlen : natural := v'length;


151   function tost(i : integer) return string is
152     variable L : line;
153     variable s, x : string(1 to 128);
154     variable n, tmp : integer := 0;
155   begin
156     tmp := i;
157     if i < 0 then tmp := -i; end if;
158     loop
159       s(128-n) := todec(tmp mod 10);
160       tmp := tmp / 10;
161       n := n+1;
162       if tmp = 0 then exit; end if;
163     end loop;
164     x(1 to n) := s(129-n to 128);
165     if i < 0 then return "-" & x(1 to n); end if;
166     return(x(1 to n));
167   end;
168