[Iverilog-devel] VHDL compile errors

[David F. <da...@ch...>]

Hi,

I'm trying to compile a VHDL package file and I'm getting these errors

../commonlib/types_common.vhd:63: syntax error
../commonlib/types_common.vhd:63: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:64: syntax error
../commonlib/types_common.vhd:64: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:67: syntax error
../commonlib/types_common.vhd:67: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:67: syntax error
../commonlib/types_common.vhd:67: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:68: syntax error
../commonlib/types_common.vhd:68: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:69: syntax error
../commonlib/types_common.vhd:69: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:69: syntax error
../commonlib/types_common.vhd:69: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:70: syntax error
../commonlib/types_common.vhd:70: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:71: syntax error
../commonlib/types_common.vhd:71: error: Syntax error in package declarative item.
../commonlib/types_common.vhd:71: syntax error
../commonlib/types_common.vhd:71: error: Syntax error in package declarative item.

63 function "-"
64 (i : integer; d : std_logic_vector)
65 return std_logic_vector;
66
 67 function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
68 function "-" (a, b : std_logic_vector) return std_logic_vector;
69 function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
70 function "+" (a, b : std_logic_vector) return std_logic_vector;
71 function "+" (d : std_logic_vector; i : std_logic) return std_logic_vector;

Looks like iverilog cannot handle overloaded functions or the string named function "-"  or "+"

David