Re: [Iverilog-devel] Supporting SystemVerilog interfaces in module ports

[Martin W. <ic...@ma...>]

Andrew Clark wrote:
> I'm attempting to append to port_declaration as follows:
> 
> /* FL4SHK code:  attempt to support interfaces as module ports */
>   | attribute_list_opt IDENTIFIER gate_instance
> 	{
> 		perm_string type_name = lex_strings.make($2);
> 		// Need more stuff here
> 		delete[]$2;
> 	}
> 
> 
> The "Need more stuff here" part is what I think I need help with. What kind
> of stuff do you need to do to handle the gate_instance part, and how do you
> use the IDENTIFIER portion as an interface type name?

Use the pform_modules map (in pform.cc) to convert type_name to a Module*. 
Module::is_interface will tell you if it really is an interface (see Module.h).

I don't think you want gate_instance in the module port declaration. It 
should be another IDENTIFIER that is the formal name for the module port. 
You need to add that name, along with the interface reference (Module*), to 
the enclosing module's list of ports (Module::ports). You are going to need 
to make some changes to the compiler's internal classes to let you do that.