[Iverilog-devel] Supporting SystemVerilog interfaces in module ports

[Andrew C. <lav...@gm...>]

For reference, here is a link to the original Github issue issue:
https://github.com/steveicarus/iverilog/issues/200

I'll go ahead and repeat the last code-related message I sent to it here.


I'm attempting to append to port_declaration as follows:

/* FL4SHK code:  attempt to support interfaces as module ports */
 | attribute_list_opt IDENTIFIER gate_instance
	{
		perm_string type_name = lex_strings.make($2);
		// Need more stuff here
		delete[]$2;
	}


The "Need more stuff here" part is what I think I need help with. What kind
of stuff do you need to do to handle the gate_instance part, and how do you
use the IDENTIFIER portion as an interface type name?