[Iverilog-devel] Simulation in iverilog producing different values when compared to Xilinx simulator

[Sab VS <sab...@gm...>]

Hi,

I am currently trying to debug a piece of code which is not working
correctly in the iverilog simulator.

The code shows that the mem_write_data changes every clock cycle.

However, the mem_0 is not changing. I am writing into mem_0 using the
following

mem_0[addr_block]<=mem_write_data[2*`PIXEL_WIDTH-1:0]

In Xilinx I see the expected value. Is this an iverilog problem or am I
doing something wrong?

I have created a short gist
https://gist.github.com/raiderark/9a857fc48d5ce9bac9bfa5b54acc3e9c . Please
comment out the unused modules in order to compile.

Could someone please help me out?