Re: [Iverilog-devel] Support for resistive verilog primitives

[Martin W. <ic...@ma...>]

I've added support for rtran switches in development. I've also implemented 
the supply->strong strength reduction for non-resistive switches (including 
nmos/pmos/cmos devices) and backported that fix to v10.

Dan Moore wrote:
> Forwarding an email reply from Cary about this.
> 
> It doesn't appear that the verilog primitive rtran is supported in the
> compiler.  The following is with the latest code available on github:
> 
> 
>> iverilog -V 2> /dev/null | head -n 1
> Icarus Verilog version 11.0 (devel) (s20150603-538-ge7a9662)
> 
> 
>> iverilog rtran_tb.v
> rtran_tb.v:14: tgt-vvp sorry: resistive switch modeling is not currently
> supported.
> error: Code generation had 1 error(s).
> 
> 
> Dan
> 
> 
> 
> 
> 
> ---------- Forwarded message ----------
> From: Cary R. <cy...@ya...>
> Date: Sun, Feb 11, 2018 at 6:24 PM
> Subject: Re: admin authorization to submit feature request
> To: ca...@us..., "moo...@us..." <
> moo...@us...>
> 
> 
> Hi Dan,
> 
> []
> 
> I looked at this quickly and noted a couple things. It looks like the
> resistive MOS devices are already implemented though I did not check their
> functionality. The compiler already supports resistive tran statements, but
> the simulation runtime (vvp) does not. I created a quick test case and
> noticed that there is actually a bug in the non-resistive tran devices
> related to the strength reduction of a supply value to strong. It looks
> like this would be easy to fix when adding resistive support. I believe the
> basics are that when resolving what value to push the resolution functions
> need to know if the resolution is a normal resolution (no strength
> modification), resolving a tran (supply -> strong) or resolving a resistive
> tran (decrement the strength by one) so that it can update the resolved
> strength appropriately. I believe it then needs to resolve this with the
> individual tran ports. It looks like it currently finds a single value and
> pushes it to both tran ports. Something like the following:
> 
> find tran resolved value using correct tran/rtran rules.
> use normal resolution to resolve the above value with the individual port
> value and push that to the port if it is different than the current value.
> 
> Post to the iverilog-devel mailing list if you need any help or would like
> input from the other developers.
> 
> Here is a simple example that can easily be switched to a rtran statement
> so see how the strength is reduced. If you run this as is you will notices
> that all the values on the switch outputs are also supply which is wrong.
> They should be strong except for the first value which is set by the assign
> statement.
> 
> module top;
>     wire sp_pin;
>     wire st_pin;
>     wire pl_pin;
>     wire lc_pin;
>     wire wk_pin;
>     wire mc_pin;
>     wire sc_pin;
>     wire sc_out;
> 
>     reg ctl;
>     reg in;
> 
>     assign (supply1, supply0) sp_pin = in;
> 
>     tranif1 (sp_pin, st_pin, ctl);
>     tranif1 (st_pin, pl_pin, ctl);
>     tranif1 (pl_pin, lc_pin, ctl);
>     tranif1 (lc_pin, wk_pin, ctl);
>     tranif1 (wk_pin, mc_pin, ctl);
>     tranif1 (mc_pin, sc_pin, ctl);
>     tranif1 (sc_pin, sc_out, ctl);
> 
>     initial begin
>        ctl = 1'b0;
>        in = 1'b0;
> 
>        #1;
>        $display("SPI: %v, SP: %v, ST: %v, PL: %v, LC: %v, WK: %v, MC: %v,
> SC: %v",
>                 sp_pin, st_pin, pl_pin, lc_pin, wk_pin, mc_pin, sc_pin,
> sc_out);
> 
>        ctl = 1'b1;
> 
>        #1;
>        $display("SPI: %v, SP: %v, ST: %v, PL: %v, LC: %v, WK: %v, MC: %v,
> SC: %v",
>                 sp_pin, st_pin, pl_pin, lc_pin, wk_pin, mc_pin, sc_pin,
> sc_out);
> 
>        in = 1'b1;
> 
>        #1;
>        $display("SPI: %v, SP: %v, ST: %v, PL: %v, LC: %v, WK: %v, MC: %v,
> SC: %v",
>                 sp_pin, st_pin, pl_pin, lc_pin, wk_pin, mc_pin, sc_pin,
> sc_out);
> 
>     end
> 
> endmodule
> 
> I would expect a version of this for rtranif1, rtranif0 (swap the control
> state) and rtran (remove the control).
> 
> Let me know of you have any questions.
> 
> Cary
> 
> On Friday, February 9, 2018, 10:31:22 AM PST, moo...@us...
> <moo...@us...> wrote:
> 
> 
> Hello, I would like to submit a feature request, specifically support for
> resistive verilog primitives. I may even investigate helping to provide
> code to implement this.
> 
> Thank you,
> 
> Dan Moore
> https://www.linkedin.com/in/danlmoore/
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